AD9822

Rev. B | Page 17 of 20

APPLICATIONS

CIRCUIT AND LAYOUT RECOMMENDATIONS

Figure 16 shows the recommended circuit configuration for

3-channel CDS mode operation. The recommended input

coupling capacitor value is 0.1 µF (see the Circuit Operation

section). A single ground plane is recommended for the

AD9822. A separate power supply may be used for DRVDD,

the digital driver supply, but this supply pin should still be

decoupled to the same ground plane as the rest of the AD9822.

The loading of the digital outputs should be minimized, either

by using short traces to the digital ASIC or by using external

digital buffers. To minimize the effect of digital transients

during major output code transitions, the falling edge of

CDSCLK2 should occur coincident with or before the rising

edge of ADCCLK (see Figure 3 through Figure 6 for timing).

All 0.1 µF decoupling capacitors should be located as close as

possible to the AD9822 pins. When operating in single-channel

mode, the unused analog inputs should be grounded.

Figure 17 shows the recommended circuit configuration for

3-channel SHA mode. All of the above considerations also apply

for this configuration, except that the analog input signals are

directly connected to the AD9822 without the use of coupling

capacitors. The analog input signals must already be dc-biased

between 0 V and 2 V (see the Circuit Operation section).

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD9822

CDSCLK1

AVDD

CDSCLK2

ADCCLK

OEB

DRVDD

DRVSS

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

AVSS

VINR

OFFSET

VING

CML

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

SDATA

3

CLOCK INPUTS

8

DATA OUTPUTS

0.1

µF

3

SERIAL INTERFACE

0.1

µF

5V/3V

5V

0.1

µF

0.1

µF

0.1

µF

0.1

µF

RED INPUT

GREEN INPUT

BLUE INPUT

0.1

µF

0.1

µF

1.0

µF

0.1

µF

0.1

µF

+

10

µF

5V

0.1

µF

Figure 16. Recommended Circuit Configuration, 3-Channel CDS Mode

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD9822

CDSCLK1

AVDD

CDSCLK2

ADCCLK

OEB

DRVDD

DRVSS

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

AVSS

VINR

OFFSET

VING

CML

VINB

CAPT

CAPB

AVSS

AVDD

SLOAD

SCLK

SDATA

3

CLOCK INPUTS

8

DATA OUTPUTS

0.1

µF

3

SERIAL INTERFACE

0.1

µF

5V/3V

5V

0.1

µF

RED INPUT

GREEN INPUT

BLUE INPUT

0.1

µF

0.1

µF

0.1

µF

+

10

µF

5V

0.1

µF

Figure 17. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)