AD5247BKSZ100-R2 datasheet(15/20 Pages) AD

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Data Sheet

AD5247

Rev. F | Page 15 of 20

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A, proportional to the input voltage

at A-to-B. Unlike the polarity of VDD to GND, which must be

positive, voltage across A-to-B, W-to-A, and W-to-B can be at

either polarity.

If ignoring the effect of the wiper resistance for approximation,

connecting the Terminal A to 5 V and the Terminal B to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage

applied across Terminal A and Terminal B divided by the 128

positions of the potentiometer divider. The general equation

defining the output voltage at VW with respect to ground for any

valid input voltage applied to Terminal A and Terminal B is

128

)

(

(3)

A more accurate calculation that includes the effect of wiper

resistance, VW, is

(D)

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

rheostat mode, divider mode makes the output voltage mainly on

the ratio of Internal Resistor RWA to Internal Resistor RWB, and

not the absolute values. Therefore, the temperature drift reduces

to 15 ppm/°C.

I2C-COMPATIBLE 2-WIRE SERIAL BUS

The first byte of the AD5247 is a slave address byte (see the I2C

Interface section). It has a 7-bit slave address and an R/W bit.

The 5 kΩ and 50 kΩ options support one 7-bit slave address

while the 10 kΩ and 100 kΩ options each have three hard-coded

slave address options available (see Table 8 for a full list of slave

address locations). The extra hard coded slave addresses on the

10 kΩ and 100 kΩ options allow users to employ up to three of

these devices on one I2C bus. The seven MSBs of the slave address

are followed by 0 for a write command or 1 to place the device

in read mode.

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 33). The

following byte is the slave address byte, consisting of the

7-bit slave address followed by an R/W bit (this bit determines

whether data is read from or written to the slave device). The

slave, whose address corresponds to the transmitted address,

responds by pulling the SDA line low during the ninth clock

pulse (this is termed the acknowledge bit). At this stage, all

other devices on the bus remain idle while the selected

device waits for data to be written to or read from its serial

slave device. If the R/W bit is low, the master writes to the

slave device.

2. In write mode, after acknowledgement of the slave address

byte, the next byte is the data byte. Data is transmitted over

the serial bus in sequences of nine clock pulses (eight data

bits followed by an acknowledge bit). The transitions on

the SDA line must occur during the low period of SCL

and remain stable during the high period of SCL (see

Figure 33).

3. In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of

nine clock pulses (a slight difference from write mode,

where eight data bits are followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during

the high period of SCL (see Figure 34).

4. When all data bits have been read or written, a stop con-

dition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10th clock pulse to establish a stop condition

(see Figure 33). In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA

line remains high). The master then brings the SDA line

low before the 10th clock pulse, which goes high to establish

a stop condition (see Figure 34).

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing the part only

once. For example, after the RDAC has acknowledged its slave

address in the write mode, the RDAC output updates on each

successive byte. If different instructions are needed, the write/read

mode has to start again with a new slave address and data byte.

Similarly, a repeated read function of the RDAC is also allowed.

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