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ADRF6750ACPZ-R7 Datasheet(PDF) 3 Page - Analog Devices

Part # ADRF6750ACPZ-R7
Description  950 MHz to 1575 MHz Quadrature Modulator
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF6750ACPZ-R7 Datasheet(HTML) 3 Page - Analog Devices

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ADRF6750
Rev. A | Page 3 of
40
SPECIFICATIONS
VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz,
REFIN = 10 MHz, PFD = 20 MHz, loop bandwidth = 50 kHz, and LOMONx is off, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF OUTPUT
RFOUT pin
Operating Frequency Range
950
1575
MHz
Nominal Output Power
VIQ = 0.9 V p-p differential
−1.6
dBm
Gain Flatness
Any 40 MHz
±0.5
dB
Output P1dB
8.5
dBm
Output IP3
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = −6 dBm per tone
23
dBm
Output Return Loss
Attenuator setting = 0 dB
−12
dB
LO Carrier Feedthrough
Attenuator setting = 0 dB to 47 dB
−45
dBc
2× LO Carrier Feedthrough
Attenuator setting = 0 dB to 47 dB
−45
dBm
Sideband Suppression
−45
dBc
Noise Floor
I/Q inputs = 0 V p-p differential, Attenuator setting = 0 dB
−162
dBm/Hz
Attenuator setting = 0 dB to 21 dB, carrier offset = 15 MHz
−147
dBc/Hz
Attenuator setting = 21 dB to 47 dB, carrier offset = 15 MHz
−170
dBm/Hz
Harmonics
−60
dBc
REFERENCE CHARACTERISTICS
REFIN pin
Input Frequency
With R/2 divider enabled
10
300
MHz
With R/2 divider disabled
10
165
MHz
Input Sensitivity
AC-coupled
0.4
VREG
V p-p
Input Capacitance
10
pF
Input Current
±100
μA
CHARGE PUMP
ICP Sink/Source
Programmable
High Value
With RSET = 4.7 kΩ
5
mA
Low Value
312.5
μA
Absolute Accuracy
With RSET = 4.7 kΩ
4.0
%
RSET Value
4.7
VCO Gain
KVCO
25
MHz/V
SYNTHESIZER SPECIFICATIONS
Frequency Resolution
1
Hz
Spurs
Integer boundary < loop bandwidth
−55
dBc
>10 MHz offset from carrier
−85
dBc
Phase Noise1
Frequency = 950 MHz to 1575 MHz
100 Hz offset
−80
dBc/Hz
1 kHz offset
−88
dBc/Hz
10 kHz offset
−93
dBc/Hz
100 kHz offset
−107
dBc/Hz
1 MHz offset
−133
dBc/Hz
>15 MHz offset
−152
dBc/Hz
Integrated Phase Noise1
1 kHz to 8 MHz integration bandwidth
0.4
°rms
Frequency Settling1
Maximum frequency error = 100 Hz
170
μs
Maximum Frequency Step for
No Autocalibration
Frequency step with no autocalibration routine;
Register CR24, Bit 0 = 1
100
kHz
Phase Detector Frequency
10
30
MHz



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