ADV7202 datasheet(21/28 Pages) AD

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REV. 0

ADV7202

–21–

TIMING REGISTER

TR (TR00–TR07)

(Address (SR4–SR0) = 0AH)

Figure 25 shows the various operations under the control of the

Timing Register.

TR BIT DESCRIPTION

Crystal Oscillator Circuit (TR00)

If this bit is set to “0,” the internal oscillator circuit will be

disabled. Disabling the oscillator circuit is possible when an

external clock module is used, thus saving power.

ADC Bias Currents (TR01)

If this bit is set to “1,” all analog bias currents will be doubled.

Duty Cycle Equalizer (TR03)

When this bit is set to “1,” the clock duty cycle equalizer circuit

is active. This will only have an effect on the ADC operation.

The digital core clock will not be affected.

Clock Delay (TR05–TR06)

Using these two bits, it is possible to insert a delay in the clock

signal to the digital core. These bits control the insertion of

the delay.

Reserved (TR02, TR04, TR07)

Zero must be written to the bits in these registers.

TR01

TR02

TR04

TR05

TR06

ZERO MUST BE

WRITTEN TO

THIS BIT

TR07

TR03

TR00

DISABLE

1ENABLE

CRYSTAL

OSCILLATOR CIRCUIT

TR06

TR05

0ns

4ns

6ns

8ns

CLOCK DELAY

TR03

INACTIVE

1ACTIVE

DUTY CYCLE

EQUALIZER

TR01

NORMAL

DOUBLE

ADC BIAS

CURRENTS

ZERO MUST BE

WRITTEN TO

THIS BIT

ZERO MUST BE

WRITTEN TO

THIS BIT

TR04

TR02

TR07

Figure 25. Timing Register 0

VREF ADJUST REGISTER

VR (VR00–VR07)

(Address (SR4–SR0) = 0BH)

Figure 26 shows the various operations under the control of the

VREF Adjust Register.

VR BIT DESCRIPTION

Reserved (VR00)

This register is reserved and “1” must be written to this bit.

Reserved (VR01–VR03)

Zero must be written to these registers.

ADC Reference Voltage Adjust (VR04–VR06)

By setting the value of this 3-bit word, it is possible to trim the

ADC internal voltage reference VREFADC.

Reserved (VR07)

Zero must be written to this register.

VR01

VR07

VR02

VR04

VR05

VR06

ZERO MUST BE

WRITTEN TO

THIS BIT

VR07

VR03

VR00

VR06 VR05

VR04

0DEFAULT NOMINAL

+14mV

+28mV

+42mV

–14mV

–28mV

–42mV

–56mV

ADC REFERENCE VOLTAGE ADJUST

ZERO MUST BE

WRITTEN TO

THESE BITS

VR03–VR01

ONE MUST BE

WRITTEN TO

THIS BIT

VR00

Figure 26. ADC VREF Register

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