MPC8306S datasheet(7/70 Pages) FREESCALE

7 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Input voltage

DDR2 DRAM signals

MVIN

–0.3 to (GVDD +0.3)

DDR2 DRAM reference

MVREF

–0.3 to (GVDD +0.3)

Local bus, DUART, SYS_CLK_IN,

system control and power

management, I2C, SPI, and JTAG

signals

OVIN

–0.3 to (OVDD +0.3)

Storage temperature range

TSTG

–55to150

C—

Notes:

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

power-on reset and power-down sequences.

Table 1. Absolute Maximum Ratings1 (continued)

Characteristic

Symbol

Max Value

Unit

Notes

MPC8306S Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc