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DF1704E/2K Datasheet(PDF) 10 Page - Texas Instruments |
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DF1704E/2K Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 20 page  DF1704 10 SBAS099A Figures 8 through 10 show more details regarding the control port data format and timing requirements. The data format for the control port is 16-bit, MSB-first, with Bit B15 being the MSB. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 MODE2 res res res res res A1 A0 res res OW1 OW0 IW1 IW0 res DEM MUT MODE3 res res res res res A1 A0 res SF1 SF0 CKO res SRO ATC LRP I2S B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ML MC MD FIGURE 8. Internal Mode Control Registers. FIGURE 9. Software Interface Format. PIN PIN NAME NUMBER DESCRIPTION RESV 13 Reserved, Not Used LRIP 12 LRCIN Polarity LRIP = L: LRCIN= H = Left Channel, LRCIN= L = Right Channel LRIP = H: LRCIN= L = Left Channel, LRCIN = H = Right Channel CKO 11 CLKO Output Frequency CKO = H: CLKO Frequency = XTI/2 CKO = L: CLKO Frequency = XTI MUTE 15 Soft Mute Control: H = Mute Off, L = Mute On I2S 3 Input Data Format Controls IW0 4 IW1 5 I2S IW1 IW0 INPUT FORMAT L L L 16-Bit, Standard, MSB-First, Right-Justified L L H 20-Bit, Standard, MSB-First, Right-Justified L H L 24-Bit, Standard, MSB-First, Right-Justified L H H 24-Bit, MSB-First, Left-Justified H L L 16-Bit, I2S H L H 24-Bit, I2S SRO 27 Digital Filter Roll-Off: H = Slow, L = Sharp OW0 19 Output Data Word Length Controls OW1 20 OW1 OW0 OUTPUT FORMAT L L 16-Bit, MSB-First L H 18-Bit, MSB-First H L 20-Bit, MSB-First H H 24-Bit, MSB-First SF0 17 Sample Rate Selection for the Digital De-Emphasis Control SF1 18 SF1 SF0 SAMPLING RATE L L 44.1kHz L H Reserved, Not Used H L 48kHz H H 32kHz DEM 16 Digital De-Emphasis: H = On, L = Off TABLE IV. Hardware Mode Controls. REGISTER BIT NAME NAME DESCRIPTION MODE0 AL[7:0] Attenuation Data for the Left Channel LDL Attenuation Load Control for the Left Channel A[1:0] Register Address res Reserved MODE1 AR[7:0] Attenuation Data for the Right Channel LDL Attenuation Load Control for the Right Channel A[1:0] Register Address res Reserved MODE2 MUT Soft Mute Control DEM Digital De-Emphasis Control IW[1:0] Input Data Format and Word Length OW[1:0] Output Data Word Length A[1:0] Register Address res Reserved MODE3 I2S Input Data Format (I2S or Standard/Left-Justified) LRP LRCIN Polarity ATC Attenuator Control, Dependent or Independent SRO Digital Filter Roll-Off Selection (sharp or slow) CKO CLKO Frequency Selection (XTI or XTI ÷ 2) SF[1:0] Sample Rate Selection for De-Emphasis Function A[1:0] Register Address res Reserved NOTE: All reserved bits should be programmed to 0. TABLE V. Internal Register Mapping. Register Addressing A[1:0], bits B10 and B9 of the 16-bit control data word, are used to indicate the register address to be written to by the current control port write cycle. Table VI shows how to address the internal registers using bits A[1:0] of registers MODE0 through MODE3. A1 A0 REGISTER SELECTED 0 0 MODE0 0 1 MODE1 1 0 MODE2 1 1 MODE3 TABLE VI. Internal Register Addressing. |
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