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DSPIC30F2011AT-30I/PF Datasheet(PDF) 230 Page - Microchip Technology |
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DSPIC30F2011AT-30I/PF Datasheet(HTML) 230 Page - Microchip Technology |
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230 / 238 page  dsPIC30F6011A/6012A/6013A/6014A DS70143C-page 228 Preliminary © 2006 Microchip Technology Inc. MCU and DSP (MAC Class) Instructions Example..... 34 Memory Map ............................................................... 31 Memory Map for dsPIC30F6011A/6013A ................... 32 Memory Map for dsPIC30F6012A/6014A ................... 33 Near Data Space ........................................................ 35 Software Stack ............................................................ 35 Spaces ........................................................................ 31 Width ........................................................................... 34 Data Converter Interface (DCI) Module ............................ 123 Data EEPROM Memory ...................................................... 57 Erasing ........................................................................ 58 Erasing, Block ............................................................. 58 Erasing, Word ............................................................. 58 Protection Against Spurious Write .............................. 61 Reading....................................................................... 57 Write Verify ................................................................. 61 Writing ......................................................................... 59 Writing, Block .............................................................. 60 Writing, Word .............................................................. 59 DC Characteristics ............................................................ 175 Brown-out Reset ............................................... 182, 183 I/O Pin Input Specifications ....................................... 181 I/O Pin Output Specifications .................................... 181 Idle Current (IIDLE) .................................................... 178 Low-Voltage Detect................................................... 181 LVDL ......................................................................... 182 Operating Current (IDD)............................................. 177 Power-Down Current (IPD) ........................................ 179 Program and EEPROM............................................. 183 DCI Module Bit Clock Generator................................................... 127 Buffer Alignment with Data Frames .......................... 129 Buffer Control ............................................................ 123 Buffer Data Alignment ............................................... 123 Buffer Length Control ................................................ 129 COFS Pin .................................................................. 123 CSCK Pin .................................................................. 123 CSDI Pin ................................................................... 123 CSDO Mode Bit ........................................................ 130 CSDO Pin ................................................................. 123 Data Justification Control Bit ..................................... 128 Device Frequencies for Common Codec CSCK Frequencies (Table)............................... 127 Digital Loopback Mode ............................................. 130 Enable ....................................................................... 125 Frame Sync Generator ............................................. 125 Frame Sync Mode Control Bits ................................. 125 I/O Pins ..................................................................... 123 Interrupts ................................................................... 130 Introduction ............................................................... 123 Master Frame Sync Operation .................................. 125 Operation .................................................................. 125 Operation During CPU Idle Mode ............................. 130 Operation During CPU Sleep Mode .......................... 130 Receive Slot Enable Bits........................................... 128 Receive Status Bits ................................................... 129 Register Map............................................................. 132 Sample Clock Edge Control Bit................................. 128 Slave Frame Sync Operation .................................... 126 Slot Enable Bits Operation with Frame Sync ............ 128 Slot Status Bits.......................................................... 130 Synchronous Data Transfers .................................... 128 Timing Characteristics AC-Link Mode ................................................... 198 Multichannel, I2S Modes................................... 196 Timing Requirements AC-Link Mode ................................................... 198 Multichannel, I2S Modes................................... 197 Transmit Slot Enable Bits ......................................... 128 Transmit Status Bits.................................................. 129 Transmit/Receive Shift Register ............................... 123 Underflow Mode Control Bit...................................... 130 Word Size Selection Bits .......................................... 125 Development Support ....................................................... 171 Device Configuration Register Map ............................................................ 161 Device Configuration Registers ........................................ 159 FBORPOR ................................................................ 159 FBS........................................................................... 159 FGS .......................................................................... 159 FOSC........................................................................ 159 FSS........................................................................... 159 FWDT ....................................................................... 159 Device Overview . 1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73, 79, 83, 87, 91, 95, 103, 111, 123, 133, 163 Disabling the UART .......................................................... 105 Divide Support .................................................................... 18 Instructions (Table) ..................................................... 18 DSP Engine ........................................................................ 19 Multiplier ..................................................................... 21 Dual Output Compare Match Mode .................................... 88 Continuous Pulse Mode.............................................. 88 Single Pulse Mode...................................................... 88 E Electrical Characteristics .................................................. 175 AC............................................................................. 184 DC ............................................................................ 175 Enabling and Setting Up UART Setting Up Data, Parity and Stop Bit Selections ....... 105 Enabling the UART ........................................................... 105 Equations ADC Conversion Clock ............................................. 135 Baud Rate................................................................. 107 Bit Clock Frequency.................................................. 127 COFSG Period.......................................................... 125 Serial Clock Rate ...................................................... 100 Time Quantum for Clock Generation ........................ 117 Errata .................................................................................... 7 External Clock Timing Characteristics Type A, B and C Timer ............................................. 192 External Clock Timing Requirements ............................... 185 Type A Timer ............................................................ 192 Type B Timer ............................................................ 193 Type C Timer ............................................................ 193 External Interrupt Requests ................................................ 49 F Fast Context Saving ........................................................... 49 Flash Program Memory ...................................................... 51 Control Registers ........................................................ 52 NVMADR ............................................................ 52 NVMADRU ......................................................... 52 NVMCON............................................................ 52 NVMKEY ............................................................ 52 |
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