DSPIC30F2011AT-30ESLASHS datasheet(223/238 Pages) MICROCHIP

223 / 238 page

Preliminary

DS70143C-page 221

dsPIC30F6011A/6012A/6013A/6014A

APPENDIX A:

REVISION HISTORY

Revision A (January 2005)

Original data sheet for dsPIC30F6011A, 6012A, 6013A

and 6014A devices.

Revision B (September 2005)

Revision B of this data sheet reflects these changes:

• 12-Bit ADC allows up to 200 ksps sampling rate

(see Section 19.6 “Selecting the ADC Conver-

sion Clock” and Section 19.7 “ADC Speeds”),

• FRC Oscillator revised to allow tuning in ±0.75%

increments (see Section 20.2.5 “Fast RC Oscil-

lator (FRC)” and Table 20-4).

• Revised electrical characteristics:

- Operating Current (IDD) (see Table 23-5)

- Idle Current (IIDLE) (see Table 23-6)

- Power-Down Current (IPD) (seeTable 23-7)

- Brown-Out Reset (BOR) (see Table 23-11)

- External Clock Timing Requirements (see

Table 23-14)

- PLL Clock Timing Specifictation (VDD = 2.5-

5.5 V) (see Table 23-15)

- PLL Jitter (seeTable 23-16 )

- Internal FRC Jitter Accuracy and Drift (see

Table 23-18)

- 12-Bit ADC Module Specifications (see

Table 23-38)

- 12-Bit ADC Conversion Timing Requirements

(see Table 23-39)

Revision C (October 2006)

Revision C of this data sheet reflects these changes:

• BSRAM and SSRAM SFRs added for Data RAM

protection (see Section 3.2.7 “Data Ram Protec-

tion Feature”)

• Added INTTREG register (see Section 5.0

“Interrupts”)

• Revised I2C Slave Addresses (see Table 15-1)

• Base Instruction CP1 removed from instruction

set (see Table 21-2)

• Revised electrical characteristics:

- Operating Current (IDD) (see Table 23-5)

- Idle Current (IIDLE) (see Table 23-6)

- Power-Down Current (IPD) (seeTable 23-7)

- I/O Pin Input Specifications (see Table 23-8)

- Brown-Out Reset (BOR) (see Table 23-11)

- Watchdog Timer (see Table 23-21)

DSPIC30F2011AT-30E/S Datasheet(PDF) 223 Page - Microchip Technology

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