DSPIC30F2011AT-30ESLASHS datasheet(149/238 Pages) MICROCHIP

149 / 238 page

Preliminary

DS70143C-page 147

dsPIC30F6011A/6012A/6013A/6014A

20.2.2

OSCILLATOR START-UP TIMER

(OST)

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator

Start-up Timer is included. It is a simple 10-bit counter

that counts 1024 TOSC cycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as TOST. The TOST time is

involved every time the oscillator has to restart (i.e., on

POR, BOR and wake-up from Sleep). The Oscillator

Start-up Timer is applied to the LP, XT, XTL and HS

Oscillator modes (upon wake-up from Sleep, POR and

BOR) for the primary oscillator.

20.2.3

LP OSCILLATOR CONTROL

Enabling the LP oscillator is controlled with two

elements:

The current oscillator group bits COSC<2:0>

The LPOSCEN bit (OSCCON register)

The LP oscillator is ON (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

• COSC<2:0> = 000 (LP selected as main oscillator)

and

• LPOSCEN = 1

Keeping the LP oscillator ON at all times allows for a

fast switch to the 32 kHz system clock for lower power

operation. Returning to the faster main oscillator will

still require a start-up time.

20.2.4

PHASE LOCKED LOOP (PLL)

The PLL multiplies the clock which is generated by the

primary oscillator. The PLL is selectable to have either

gains of x4, x8 and x16. Input and output frequency

ranges are summarized in Table 20-3.

TABLE 20-3:

PLL FREQUENCY RANGE

The PLL features a lock output, which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read-only LOCK bit in the OSCCON register.

20.2.5

FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (7.37 MHz ±2% nominal)

internal RC oscillator. This oscillator is intended to pro-

vide reasonable device operating speeds without the

use of an external crystal, ceramic resonator or RC net-

work. The FRC oscillator can be used with the PLL to

obtain higher clock frequencies.

The dsPIC30F operates from the FRC oscillator when-

ever the current oscillator selection control bits in the

OSCCON register (OSCCON<14:12>) are set to ‘001’.

The

six

bit

field

specified

TUN<3:0>

(OSCTUN<3:0>) allows the user to tune the internal

fast RC oscillator (nominal 7.37 MHz). The user can

tune the FRC oscillator within a range of ±6% in steps

of 0.75% around the factory-calibrated setting (see

Table 20-4).

If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are

set to ‘00101’, ‘00110’ or ‘00111’, then a PLL

multiplier of 4, 8 or 16 (respectively) is applied.

TABLE 20-4:

FRC TUNING

Fin

PLL

Multiplier

Fout

4 MHz-10 MHz

16 MHz-40 MHz

4 MHz-10 MHz

32 MHz-80 MHz

4 MHz-7.5 MHz

x16

64 MHz-120 MHz

Note:

When a 16x PLL is used, the FRC oscilla-

tor must not be tuned to a frequency

greater than 7.5 MHz.

TUN<3:0>

Bits

FRC Frequency

0111

+5.25%

0110

+4.50%

0101

+3.75%

0100

+3.00%

0011

+2.25%

0010

+1.50%

0001

+0.75%

0000

Center Frequency (oscillator is

running at calibrated frequency)

1111

-0.75%

1110

-1.50%

1101

-2.25%

1100

-3.00%

1011

-3.75%

1010

-4.50%

1001

-5.25%

1000

-6.00%

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