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DSPIC30F2011AT-30E/S Datasheet(PDF) 178 Page - Microchip Technology |
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DSPIC30F2011AT-30E/S Datasheet(HTML) 178 Page - Microchip Technology |
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178 / 238 page ![]() dsPIC30F6011A/6012A/6013A/6014A DS70143C-page 176 Preliminary © 2006 Microchip Technology Inc. TABLE 23-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC30F601xA-30I Operating Junction Temperature Range TJ -40 +125 °C Operating Ambient Temperature Range TA -40 +85 °C dsPIC30F601xA-20E Operating Junction Temperature Range TJ -40 +150 °C Operating Ambient Temperature Range TA -40 +125 °C Power Dissipation: Internal chip power dissipation: PD P INT + PI /O W I/O Pin power dissipation: Maximum Allowed Power Dissipation PDMAX (T J - TA)/ θ JA W TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 80-pin TQFP (14x14x1mm) θ JA 34 °C/W 1 Package Thermal Resistance, 64-pin TQFP (14x14x1mm) θ JA 34 °C/W 1 Package Thermal Resistance, 80-pin TQFP (12x12x1mm) θ JA 39 °C/W 1 Package Thermal Resistance, 64-pin TQFP (10x10x1mm) θ JA 39 °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-ja ( θ JA) numbers are achieved by package simulations. TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. Symbol Characteristic Min Typ(1) Max Units Conditions Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature DC12 VDR RAM Data Retention Voltage(3) —1.5 — V DC16 VPOR VDD Start Voltage to ensure internal Power-on Reset signal —VSS —V DC17 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 V/ms 0-5V in 0.1 sec 0-3V in 60 ms Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which VDD can be lowered without losing RAM data. P INT V DD I DD I OH ∑ – () × = P I /O V DD V OH – {} I OH × () ∑ V OL I OL × () ∑ + = |
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