DSPIC30F0010AT-20ESLASHS datasheet(155/236 Pages) MICROCHIP

155 / 236 page

DS70150C-page 153

dsPIC30F6010A/6015

21.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

21.3

Reset

The dsPIC30F differentiates between various kinds of

Reset:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during Sleep

Watchdog Timer (WDT) Reset (during normal

operation)

Programmable Brown-out Reset (BOR)

RESET

Instruction

Reset caused by trap lockup (TRAPR)

Reset caused by illegal opcode, or by using an

uninitialized W register as an Address Pointer

(IOPUWR)

Different registers are affected in different ways by

various Reset conditions. Most registers are not

affected by a WDT wake-up, since this is viewed as the

resumption of normal operation. Status bits from the

RCON register are set or cleared differently in different

Reset situations, as indicated in Table 21-5. These bits

are used in software to determine the nature of the

Reset.

A block diagram of the on-chip Reset circuit is shown in

Figure 21-2.

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

Internally generated Resets do not drive MCLR pin low.

FIGURE 21-2:

RESET SYSTEM BLOCK DIAGRAM

Byte Write “0x46” to OSCCON low

Byte Write “0x57” to OSCCON low

Byte Write

“0x78” to OSCCON high

Byte Write

“0x9A” to OSCCON high

MCLR

VDD

VDD Rise

Detect

POR

SYSRST

Sleep or Idle

Brown-out

Reset

BOREN

RESET

Instruction

WDT

Module

Digital

Glitch Filter

BOR

Trap Conflict

Illegal Opcode/

Uninitialized W Register

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