DSPIC30F0010AT-20ESLASHS datasheet(156/236 Pages) MICROCHIP

156 / 236 page

dsPIC30F6010A/6015

DS70150C-page 154

21.3.1

POR: POWER-ON RESET

A power-on event will generate an internal POR pulse

when a VDD rise is detected. The Reset pulse will occur

at the POR circuit threshold voltage (VPOR), which is

nominally 1.85V. The device supply voltage character-

istics must meet specified starting voltage and rise rate

requirements. The POR pulse will reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the

oscillator configuration fuses.

The POR circuit inserts a small delay, TPOR, which is

nominally 10

μs and ensures that the device bias

circuits are stable. Furthermore, a user selected power-

up time-out (TPWRT) is applied. The TPWRT parameter

is based on device Configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms or 64 ms. The total delay is at

device power-up TPOR + TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock, and the PC will jump to

the Reset vector.

The timing for the SYSRST signal is shown in

Figure 21-3 through Figure 21-5.

FIGURE 21-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 21-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

TPWRT

TOST

VDD

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

MCLR

TPWRT

TOST

VDD

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

MCLR

DSPIC30F0010AT-20E/S Datasheet(PDF) 156 Page - Microchip Technology

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