0.01

µF

0.01

µF

CLKP

CLKM

Square Wave

or Sine Wave

(3V

ADS5520

0.01

µF

CLKP

CLKM

0.01

µF

Differential Square Wave

or Sine Wave

(3V

ADS5520

100

95

90

85

80

75

70

65

60

Clock Duty Cycle

− %

35

40

50

45

55

65

60

SFDR

SNR

f

ADS5520

Figure 46. AC-Coupled, Single-Ended Clock Input

The ADS5520 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this

case, it is best to connect both clock inputs to the differential input clock signal with 0.01-

µF capacitors, as shown

in Figure 47.

Figure 47. AC-Coupled, Differential Clock Input

For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the

internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty

cycle should be provided. Figure 48 shows the performance variation of the ADC versus clock duty cycle.

Figure 48. AC Performance vs Clock Duty Cycle

Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When

using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a

differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute

maximum ratings of the ADC clock input. Figure 49 shows the performance variation of the device versus input

clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the

ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.

Copyright © 2004–2008, Texas Instruments Incorporated

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