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TAS5706APAPR Datasheet(PDF) 26 Page - Texas Instruments |
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TAS5706APAPR Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 71 page ![]() Left-Justified 23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelLeft-JustifiedStereoInput T0034-02 4 5 9 8 1 4 5 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 4 5 9 8 1 4 5 1 0 0 0 SCLK TAS5706A TAS5706B SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. NOTE: All data presented in 2s-complement form with MSB first. Figure 33. Left-Justified 64-fS Format 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5706A TAS5706B TAS5706A is Not Recommended for New Designs |
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