PE43404 datasheet(2/11 Pages) PSEMI

2 / 11 page

Product Specification

PE43404

Page 2 of 11

Document No. 70-0258-02

│ UltraCMOS™ RFIC Solutions

N/C

RF1

Data

Clock

GND

Vss/GND

P/S

RF2

20-lead

QFN

4x4mm

Exposed Solder Pad

Table 2. Pin Descriptions

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ device, observe

the same precautions that you would use with other

ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rate specified in Table 3.

Exposed Solder Pad Connection

The exposed solder pad on the bottom of the

package must be grounded for proper device

operation.

Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with

an external series capacitor.

2. Latch Enable (LE) has an internal 100 k

Ωresistor to V

DD.

3. Connect pin 12 to GND to enable internal negative

voltage generator. Connect pin 12 to VSS (-VDD) to

bypass and disable internal negative voltage generator.

4. Place a 10 k

Ωresistor in series, as close to pin as

possible to avoid frequency resonance. See “Resistor on

3” paragraph

Figure 15. Pin Configuration (Top View)

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Switching Frequency

The PE43404 has a maximum 25 kHz switching rate.

No.

Name

Description

N/C

No connect

RF1

RF port (Note 1).

Data

Serial interface data input (Note 4).

Clock

Serial interface clock input.

Latch Enable input (Note 2).

VDD

Power supply pin.

N/C

No connect

PUP2

Power-up selection bit.

VDD

Power supply pin.

GND

Ground connection.

GND

Ground connection.

Vss/

GND

Negative supply voltage or GND

connection (Note 3)

P/S

Parallel/Serial mode select.

RF2

RF port (Note 1).

Attenuation control bit, 8 dB.

Attenuation control bit, 4 dB.

Attenuation control bit, 2 dB.

GND

Ground connection.

Attenuation control bit, 1 dB.

GND

Ground for proper operation

Paddle

GND

Ground for proper operation

Resistor on Pin 3

A 10 k

Ω resistor on the input to Pin 3 (see Figure 5)

will eliminate package resonance between the RF

input pin and the digital input. Specified attenuation

error versus frequency performance is dependent

upon this condition.

Table 3. Absolute Maximum Ratings

Table 4. Operating Ranges

Symbol

Parameter/Conditions

Min

Max

Units

VDD

Power supply voltage

-0.3

4.0

Voltage on any input

-0.3

VDD+

0.3

TST

Storage temperature range

-65

150

°C

Input power (50

Ω)

+30

dBm

VESD

ESD voltage (Human Body

Model)

500

Parameter

Min

Typ

Max

Units

VDD Power Supply

Voltage

2.7

3.0

3.3

IDD Power Supply

Current

100

µA

Digital Input High

0.7xVDD

Digital Input Low

0.3xVDD

Digital Input Leakage

µA

Input Power

+24

dBm

Temperature range

-40

°C

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be restricted

to the limits in the Operating Ranges table.

Operation between operating range maximum and

absolute maximum for extended periods may reduce

reliability.

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