PIC16 datasheet(56/418 Pages) MICROCHIP

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PIC16(L)F1508/9

DS40001609C-page 56

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5.4

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external oscil-

lator start-up and code execution. In applications that

make heavy use of the Sleep mode, Two-Speed Start-up

will remove the external oscillator start-up time from the

time spent awake and can reduce the overall power con-

sumption of the device. This mode allows the application

to wake-up from Sleep, perform a few instructions using

the INTOSC internal oscillator block as the clock source

and go back to Sleep without waiting for the external

oscillator to become stable.

Two-Speed Start-up provides benefits when the oscilla-

tor module is configured for LP, XT, or HS modes. The

Oscillator Start-up Timer (OST) is enabled for these

modes and must count 1024 oscillations before the oscil-

lator can be used as the system clock source.

If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock

oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters

Sleep mode, the OSTS bit of the OSCSTAT register is

set and program execution switches to the external oscil-

lator. However, the system may never operate from the

external oscillator if the time spent awake is very short.

5.4.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the following

settings:

• IESO (of the Configuration Words) = 1;

Internal/External Switchover bit (Two-Speed

Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-On Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

5.4.2

TWO-SPEED START-UP

SEQUENCE

Wake-up from Power-on Reset or Sleep.

Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>

bits of the OSCCON register.

OST enabled to count 1024 clock cycles.

OST timed out, wait for falling edge of the

internal oscillator.

OSTS is set.

System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

System clock is switched to external clock

source.

5.4.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCSTAT

external clock source, as defined by the FOSC<2:0>

bits in the Configuration Words, or the internal oscilla-

tor. See Table 5-2.

TABLE 5-3:

OSCILLATOR SWITCHING DELAYS

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCSTAT register to

remain clear.

Note:

When FSCM is enabled, Two-Speed

Start-up will automatically be enabled.

Switch From

Switch To

Oscillator Delay

Any clock source

LFINTOSC

1 cycle of each clock source

HFINTOSC

s (approx.)

ECH, ECM, ECL, EXTRC

2 cycles

LP, XT, HS

1024 Clock Cycles (OST)

Secondary Oscillator

1024 Secondary Oscillator Cycles

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