PIC18F4550ESOSQTP datasheet(145/438 Pages) MICROCHIP

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DS39632E-page 143

PIC18F2455/2550/4455/4550

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F2455/2550/4455/4550 devices all have two

CCP (Capture/Compare/PWM) modules. Each module

contains a 16-bit register, which can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register.

In 28-pin devices, the two standard CCP modules (CCP1

and CCP2) operate as described in this chapter. In

40/44-pin devices, CCP1 is implemented as an

Enhanced CCP module, with standard Capture and

Compare modes and Enhanced PWM modes. The

ECCP implementation is discussed in Section 16.0

“Enhanced Capture/Compare/PWM (ECCP) Module”.

The Capture and Compare operations described in this

chapter apply to all standard and Enhanced CCP

modules.

Note: Throughout this section and Section 16.0

“Enhanced Capture/Compare/PWM (ECCP)

Module”, references to the register and bit

names for CCP modules are referred to gener-

ically by the use of ‘x’ or ‘y’ in place of the

specific module number. Thus, “CCPxCON”

might refer to the control register for CCP1,

CCP2 or ECCP1. “CCPxCON” is used

throughout these sections to refer to the

module control register regardless of whether

the CCP module is a standard or Enhanced

implementation.

CCPxCON: STANDARD CCPx CONTROL REGISTER

U-0

R/W-0

—(1)

DCxB1

DCxB0

CCPxM3

CCPxM2

CCPxM1

CCPxM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’(1)

bit 5-4

DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty

cycle are found in CCPR1L.

bit 3-0

CCPxM3:CCPxM0: CCPx Module Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit

is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit

is set)

1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin

reflects I/O state)

1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match

(CCPxIF bit is set)

11xx =PWM mode

Note 1:

These bits are not implemented on 28-pin devices and are read as ‘0’.

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