PIC10LF322T-EMCSQTP datasheet(132/210 Pages) MICROCHIP

132 / 210 page

PIC10(L)F320/322

DS41585A-page 132

Preliminary

 2011 Microchip Technology Inc.

20.2

FIXED DUTY CYCLE (FDC) MODE

In Fixed Duty Cycle (FDC) mode, every time the

Accumulator overflows, the output is toggled. This

provides a 50% duty cycle, provided that the increment

value remains constant. For more information, see

Figure 20-2.

The FDC mode is selected by clearing the NxPFM bit

in the NCOxCON register.

20.3

PULSE FREQUENCY (PF) MODE

In Pulse Frequency (PF) mode, every time the Accu-

mulator overflows, the output becomes active for one

or more clock periods. See Section 20.3.1 “OUTPUT

PULSE WIDTH CONTROL”

for more information.

Once the clock period expires, the output returns to an

inactive state. This provides a pulsed output.

The output becomes active on the rising clock edge

immediately following the overflow event. For more

information, see Figure 20-2.

The value of the active and inactive states depends on

the Polarity bit, NxPOL in the NCOxCON register.

The PF mode is selected by setting the NxPFM bit in

the NCOxCON register.

20.3.1

OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the out-

put can vary in width by multiple clock periods. Various

pulse widths are selected with the NxPWS<2:0> bits in

the NCOxCLK register.

When the selected pulse width is greater than the

Accumulator overflow time frame, then NCOx opera-

tion is undefined.

20.4

OUTPUT POLARITY CONTROL

The last stage in the NCOx module is the output polar-

ity. The NxPOL bit in the NCOxCON register selects the

output polarity. Changing the polarity while the inter-

rupts are enabled will cause an interrupt for the result-

ing output transition.

The NCOx output can be used internally by source

code or other peripherals. This is done by reading the

NxOUT (read-only) bit of the NCOxCON register.

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