PIC10LF322T-EMCSQTP datasheet(142/210 Pages) MICROCHIP

142 / 210 page

PIC10(L)F320/322

DS41585A-page 142

Preliminary

 2011 Microchip Technology Inc.

21.1

Fundamental Operation

The CWG generates a two output complementary

waveform from one of four selectable input sources.

The off-to-on transition of each output can be delayed

from the on-to-off transition of the other output, thereby,

creating a time delay immediately where neither output

is driven. This is referred to as dead time and is covered

in Section 21.5 “Dead-Band Control”. A typical

operating waveform, with dead band, generated from a

single input signal is shown in Figure 21-2.

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. This is

referred to as auto-shutdown and is covered in

Section 21.9 “Auto-shutdown Control”

21.2

Clock Source

The CWG module allows for up to 2 different clock

sources to be selected:

• Fosc (system clock)

• HFINTOSC (16 MHz only)

The clock sources are selected using the G1CS0 bit of

the CWGxCON0 register (Register 21-1).

21.3

Selectable Input Sources

The CWG uses four different input sources to gener-

ate the complementary waveform:

•PWM1

•PWM2

•N1OUT

•LC1OUT

The input sources are selected using the GxIS<1:0>

bits in the CWGxCON1 register (Register 21-2).

21.4

Output Control

Immediately after the CWG module is enabled, the

complementary drive is configured with both CWGxA

and CWGxB drives cleared.

21.4.1

OUTPUT ENABLES

Each CWG output pin has individual output enable

control. Output enables are selected with the GxOEA

and GxOEB bits of the CWGxCON0 register. When an

output enable control is cleared, the module asserts no

control over the pin. When an output enable is set, the

override value or active PWM waveform is applied to

the pin per the port priority selection. The output pin

enables are dependent on the module enable bit,

GxEN. When GxEN is cleared, CWG output enables

and CWG drive levels have no effect.

21.4.2

POLARITY CONTROL

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active high. Clearing the output

polarity bit configures the corresponding output as

active low. However, polarity does not affect the

override levels. Output polarity is selected with the

GxPOLA and GxPOLB bits of the CWGxCON0 register.

21.5

Dead-Band Control

Dead-band control provides for non-overlapping output

signals to prevent shoot-through current in power

switches. The CWG contains two 6-bit dead-band

counters. One dead-band counter is used for the rising

edge of the input source control. The other is used for

the falling edge of the input source control.

Dead band is timed by counting CWG clock periods

from zero up to the value in the rising or falling dead-

band

counter

registers.

See

CWGxDBR

and

CWGxDBF registers (Register 21-4 and Register 21-5,

respectively).

21.6

Rising Edge Dead Band

The rising edge dead band delays the turn-on of the

CWGxA output from when the CWGxB output is turned

off. The rising edge dead-band time starts when the

rising edge of the input source signal goes true. When

this happens, the CWGxB output is immediately turned

off and the rising edge dead-band delay time starts.

When the rising edge dead-band delay time is reached,

the CWGxA output is turned on.

The CWGxDBR register sets the duration of the dead-

band interval on the rising edge of the input source

signal. This duration is from 0 to 64 counts of dead band.

Dead band is always counted off the edge on the input

source signal. A count of 0 (zero), indicates that no

dead band is present.

If the input source signal is not present for enough time

for the count to be completed, no output will be seen on

the respective output.

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