GAL22V10D-25LS datasheet(16/23 Pages) LATTICE

16 / 23 page

Specifications GAL22V10

(Vref Typical = 3.2V)

Circuitry within the GAL22V10 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q out-

puts set low after a specified time (tpr, 1μs MAX). As a result, the

state on the registered output pins (if they are enabled) will be

either high or low on power-up, depending on the programmed

polarity of the output pins. This feature can greatly simplify state

machine design by providing a known state on power-up. The

timing diagram for power-up is shown below. Because of the asyn-

chronous nature of system power-up, some conditions must be

met to guarantee a valid power-up reset of the GAL22V10. First,

the Vcc rise must be monotonic. Second, the clock input must

be at static TTL level as shown in the diagram during power up.

The registers will reset within a maximum of tpr time. As in nor-

mal system operation, avoid clocking the device until all input and

feedback path setup times have been met. The clock must also

meet the minimum pulse width requirements.

Vcc

Vref

Active Pull-up

Circuit

ESD

Protection

Circuit

ESD

Protection

Circuit

Vcc

Vcc (min.)

tpr

Internal Register

Reset to Logic "0"

Device Pin

Reset to Logic "1"

twl

tsu

Device Pin

Reset to Logic "0"

Vc c

CL K

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

Vcc

Vref

Tri-State

Control

Active Pull-up

Circuit

Feedback

(To Input Buffer)

Feedback

Data

Output

Typical Input

Typical Output

Power-Up Reset

Input/Output Equivalent Schematics

GAL22V10D-25LS Datasheet(PDF) 16 Page - Lattice Semiconductor

GAL22V10D-25LS Datasheet(HTML) 16 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL