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AAT1171

600mA Voltage-Scaling Step-Down Converter

for RF Power Amplifiers with Bypass Switch

DATA SHEET

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the AAT1171. Low

ESR/ESL X7R and X5R ceramic capacitors are ideal for

this function. To minimize stray inductance, the capaci-

tor should be placed as closely as possible to the IC. This

keeps the high frequency content of the input current

localized, minimizing EMI and input voltage ripple.

The proper placement of the input capacitor (C1) can be

seen in the evaluation board layout in Figure 4.

A laboratory test set-up typically consists of two long

wires running from the bench power supply to the eval-

uation board input voltage pins. The inductance of these

wires, along with the low-ESR ceramic input capacitor,

can create a high Q network that may affect converter

performance. This problem often becomes apparent in

the form of excessive ringing in the output voltage dur-

ing load transients with errors in loop phase and gain

measurements.

Since the inductance of a short PCB trace feeding the

input voltage is significantly lower than the power leads

from the bench power supply, most applications do not

exhibit this problem.

In applications where the input power source lead induc-

tance cannot be reduced to a level that does not affect

the converter performance, a high ESR tantalum or alu-

minum electrolytic capacitor (C3 of Figure 5) should be

placed in parallel with the low ESR, ESL bypass ceramic

capacitor. This dampens the high Q network and stabi-

lizes the system.

DAC Programming Gain

The output voltage is dynamically controlled by the DAC

input voltage. The DAC to output gain is fixed at 3. The

typical response time for a 0.2V to 1.2V pulsed signal on

the DAC input is less than 30μs. The DAC gain can be

reduced by an external resistive divider at the DAC

input, as shown in the evaluation board schematic in

Figures 2 and 3. For a DAC to output gain of 2 and R2

at 10kΩ, R1 is 4.99kΩ.

(3 - 2)10kΩ

2

R1 =

=

= 4.99kΩ

Thermal Calculations

There are three types of losses associated with the

AAT1171 step-down converter: switching losses, con-

duction losses, and quiescent current losses. Conduction

the power MOSFET devices. Switching losses are domi-

nated by the gate charge of the power MOSFET devices.

The AAT1171 main and synchronous power MOSFETs are

input voltage. At full load, assuming continuous conduc-

tion mode (CCM), a simplified form of the step-down

converter losses is given by:

es, which are dominated by the gate charge losses.

For the condition where the buck converter is at 100%

duty cycle dropout, the total device dissipation reduces

to:

es with decreasing input voltage and the associated

losses are a maximum at the minimum input voltage

(2.7V).

all vary with input voltage, the total losses should be

investigated over the complete input voltage range.

After calculating the total losses, the maximum junction

12 package which is typically 50°C/W.