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PIC24HJ128GP310 Datasheet(PDF) 205 Page - Microchip Technology |
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PIC24HJ128GP310 Datasheet(HTML) 205 Page - Microchip Technology |
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205 / 286 page  © 2007 Microchip Technology Inc. DS70175F-page 203 PIC24HJXXXGPX06/X08/X10 FIGURE 19-2: ADC2 MODULE BLOCK DIAGRAM(1) S/H + - Conversion Conversion Logic VREF+(2) AVSS AVDD ADC2 16-bit ADC Output 00000 00101 00111 01001 11110 11111 00001 00010 00011 00100 00110 01000 01010 01011 AN14 AN15 AN8 AN9 AN10 AN11 AN2 AN4 AN7 AN0 AN3 AN1 AN5 CH1(3) CH2(3) CH3(3) CH0 AN5 AN2 AN11 AN8 VREF- AN4 AN1 AN10 AN7 VREF- AN3 AN0 AN9 AN6 VREF- AN1 VREF- VREF-(2) Sample/Sequence Control Sample CH1,CH2, CH3,CH0 Input MUX Control Input Switches S/H + - S/H + - S/H + - AN6 Buffer Result Note 1: On devices with two ADC modules, AN0-AN15 can be read by either ADC1, ADC2 or both ADCs. 2: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details. 3: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. |
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