PIC24HJ128GP310 datasheet(176/286 Pages) MICROCHIP

176 / 286 page

PIC24HJXXXGPX06/X08/X10

DS70175F-page 174

An additional buffer is always committed to monitoring

the bus for incoming messages. This buffer is called the

Message Assembly Buffer (MAB).

All messages are assembled by the MAB and are trans-

ferred to the buffers only if the acceptance filter criterion

are met. When a message is received, the RBIF flag

(CiINTF<1>) will be set. The user would then need to

inspect the CiVEC and/or CiRXFUL1 register to deter-

mine which filter and buffer caused the interrupt to get

generated. The RBIF bit can only be set by the module

when a message is received. The bit is cleared by the

user when it has completed processing the message in

the buffer. If the RBIE bit is set, an interrupt will be

generated when a message is received.

18.4.2

FIFO BUFFER MODE

The ECAN module provides FIFO buffer functionality if

the buffer pointer for a filter has a value of ‘1111’. In this

mode, the results of a hit on that buffer will write to the

next available buffer location within the FIFO.

The CiFCTRL register defines the size of the FIFO. The

FSA<4:0> bits in this register define the start of the

FIFO buffers. The end of the FIFO is defined by the

DMABS<2:0> bits if DMA is enabled. Thus, FIFO sizes

up to 32 buffers are supported.

18.4.3

MESSAGE ACCEPTANCE FILTERS

The message acceptance filters and masks are used to

determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

Message Assembly Buffer (MAB), the identifier fields of

the message are compared to the filter values. If there

is a match, that message will be loaded into the

appropriate receive buffer. Each filter is associated with

a buffer pointer (FnBP<3:0>), which is used to link the

filter to one of 16 receive buffers.

The acceptance filter looks at incoming messages for

the IDE bit (CiTRBnSID<0>) to determine how to com-

pare the identifiers. If the IDE bit is clear, the message

is a standard frame and only filters with the EXIDE bit

(CiRXFnSID<3>) clear are compared. If the IDE bit is

set, the message is an extended frame, and only filters

with the EXIDE bit set are compared.

18.4.4

MESSAGE ACCEPTANCE FILTER

MASKS

The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, then that bit

will automatically be accepted regardless of the filter

bit. There are three programmable acceptance filter

masks associated with the receive buffers. Any of

these three masks can be linked to each filter by select-

ing the desired mask in the FnMSK<1:0> bits in the

appropriate CiFMSKSELn register.

18.4.5

RECEIVE ERRORS

The CAN module will detect the following receive

errors:

• Cyclic Redundancy Check (CRC) Error

• Bit Stuffing Error

• Invalid Message Receive Error

These receive errors do not generate an interrupt.

However, the receive error counter is incremented by

one in case one of these errors occur. The RXWAR bit

(CiINTF<9>) indicates that the receive error counter

has reached the CPU warning limit of 96 and an

interrupt is generated.

18.4.6

RECEIVE INTERRUPTS

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

• Receive Interrupt:

A message has been successfully received and

loaded into one of the receive buffers. This inter-

rupt is activated immediately after receiving the

End-of-Frame (EOF) field. Reading the RXnIF flag

will indicate which receive buffer caused the

interrupt.

• Wake-up Interrupt:

The CAN module has woken up from Disable

mode or the device has woken up from Sleep

mode.

• Receive Error Interrupts:

A receive error interrupt will be indicated by the

ERRIF bit. This bit shows that an error condition

occurred. The source of the error can be deter-

mined by checking the bits in the CAN Interrupt

Flag register, CiINTF.

- Invalid Message Received:

If any type of error occurred during reception of

the last message, an error will be indicated by

the IVRIF bit.

- Receiver Overrun:

The RBOVIF bit (CiINTF<2>) indicates that an

overrun condition occurred.

- Receiver Warning:

The RXWAR bit indicates that the receive error

counter (RERRCNT<7:0>) has reached the

warning limit of 96.

- Receiver Error Passive:

The RXEP bit indicates that the receive error

counter has exceeded the error passive limit of

127 and the module has gone into error passive

state.

PIC24HJ128GP310 Datasheet(PDF) 176 Page - Microchip Technology

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