PIC24HJ128GP310 datasheet(222/286 Pages) MICROCHIP

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PIC24HJXXXGPX06/X08/X10

DS70175F-page 220

20.2

On-Chip Voltage Regulator

All of the PIC24HJXXXGPX06/X08/X10 devices power

their core digital logic at a nominal 2.5V. This may cre-

ate an issue for designs that are required to operate at

a higher typical voltage, such as 3.3V. To simplify sys-

tem

design,

all

devices

the

PIC24HJXXXGPX06/X08/X10 family incorporate an

on-chip regulator that allows the device to run its core

logic from VDD.

The regulator provides power to the core from the other

VDD pins. The regulator requires that a low-ESR (less

than 5 ohms) capacitor (such as tantalum or ceramic)

be connected to the VDDCORE/VCAP pin (Figure 20-1).

This helps to maintain the stability of the regulator. The

recommended value for the filter capacitor is provided

in TABLE 23-13: “Internal Voltage Regulator Speci-

fications” located in Section 23.1 “DC Characteris-

tics”.

On a POR

, it takes approximately 20 μs for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 20-1:

ON-CHIP VOLTAGE

REGULATOR(1)

CONNECTIONS

20.3

BOR: Brown-Out Reset

The BOR (Brown-out Reset) module is based on an

internal voltage reference circuit that monitors the reg-

ulated voltage VDDCORE. The main purpose of the BOR

module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (i.e.,

missing portions of the AC cycle waveform due to bad

power transmission lines or voltage sags due to exces

ive current draw when a large inductive load is turned

on).

A BOR will generate a Reset pulse which will reset the

device. The BOR will select the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>). Furthermore, if an oscillator mode is

selected, the BOR will activate the Oscillator Start-up

Timer (OST). The system clock is held until OST

expires. If the PLL is used, then the clock will be held

until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) will be

applied before the internal Reset is released. If TPWRT

= 0 and a crystal oscillator is being used, then a nomi-

nal delay of TFSCM = 100 ìs is applied. The total delay

in this case is TFSCM.

The BOR Status bit (RCON<1>) will be set to indicate

that a BOR has occurred. The BOR circuit, if enabled,

continues to operate while in Sleep or Idle modes and

will reset the device should VDD fall below the BOR

threshold voltage.

Note 1:

These are typical operating voltages. Refer

to TABLE 23-13: “Internal Voltage Regu-

lator Specifications” located in

Section 23.1 “DC Characteristics” for the

full operating ranges of VDD and VDDCORE.

VDD

VDDCORE/VCAP

VSS

PIC24H

3.3V

μF

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