PIC24HJ128GP310 datasheet(67/286 Pages) MICROCHIP

67 / 286 page

DS70175F-page 65

PIC24HJXXXGPX06/X08/X10

6.0

INTERRUPT CONTROLLER

The PIC24HJXXXGPX06/X08/X10 interrupt controller

reduces the numerous peripheral interrupt request

signals to a single interrupt request signal to the

PIC24HJXXXGPX06/X08/X10 CPU. It has the follow-

ing features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

6.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 6-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors consisting of

8 nonmaskable trap vectors plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority; this priority is linked to their position in the

vector table. All other things being equal, lower

addresses have a higher natural priority. For example,

the interrupt associated with vector 0 will take priority

over interrupts at any other vector address.

PIC24HJXXXGPX06/X08/X10 devices implement up

to 61 unique interrupts and 5 nonmaskable traps.

These are summarized in Table 6-1 and Table 6-2.

6.1.1

ALTERNATE VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 6-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to

switch between an application and a support environ-

ment without requiring the interrupt vectors to be

reprogrammed. This feature also enables switching

between applications for evaluation of different soft-

ware algorithms at run time. If the AIVT is not needed,

the AIVT should be programmed with the same

addresses used in the IVT.

6.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24HJXXXGPX06/X08/X10 device clears its

registers in response to a Reset which forces the PC to

zero. The digital signal controller then begins program

execution at location 0x000000. The user programs a

GOTO instruction at the Reset address which redirects

program execution to the appropriate start-up routine.

Note:

This data sheet summarizes the features

of this group of PIC24HJXXXGPX06/X08/

X10 devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to the “PIC24H Family Reference

Manual”. Refer to the Microchip web site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

PIC24HJ128GP310 Datasheet(PDF) 67 Page - Microchip Technology

PIC24HJ128GP310 Datasheet(HTML) 67 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL