PIC24HJ128GP310 datasheet(238/286 Pages) MICROCHIP

238 / 286 page

PIC24HJXXXGPX06/X08/X10

DS70175F-page 236

23.1

DC Characteristics

TABLE 23-1:

OPERATING MIPS VS. VOLTAGE

Characteristic

VDD Range

(in Volts)

Temp Range

(in °C)

Max MIPS

PIC24HJXXXGPX06/X08/X10

DC5

3.0-3.6V

-40°C to +85°C

TABLE 23-2:

THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24HJXXXGPX06/X08/X10

Operating Junction Temperature Range

-40

—

+125

°C

Operating Ambient Temperature Range

-40

—

+85

°C

Power Dissipation:

Internal chip power dissipation:

PINT = VDD x (IDD –

Σ IOH)

PINT + PI/O

I/O Pin Power Dissipation:

I/O =

Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/

θJA

TABLE 23-3:

THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 100-pin TQFP (14x14x1 mm)

θJA

48.4

—

°C/W

Package Thermal Resistance, 100-pin TQFP (12x12x1 mm)

θJA

52.3

—

°C/W

Package Thermal Resistance, 64-pin TQFP (10x10x1 mm)

θJA

38.3

—

°C/W

Note 1:

Junction to ambient thermal resistance, Theta-JA (

θJA) numbers are achieved by package simulations.

TABLE 23-4:

DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature

-40°C

≤ TA ≤ +85°C for Industrial

Param

No.

Symbol

Characteristic

Min

Typ(1) Max

Units

Conditions

Operating Voltage

DC10

Supply Voltage

VDD

3.0

—

3.6

DC12

VDR

RAM Data Retention Voltage(2)

1.1

1.3

1.8

DC16

VPOR

VDD Start Voltage(4)

to ensure internal

Power-on Reset signal

——

Vss

DC17

SVDD

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.03

—

V/ms 0-3.0V in 0.1s

DC18

VCORE

VDD Core(3)

Internal regulator voltage

2.25

—

2.75

Voltage is dependent on load,

temperature and VDD

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: This is the limit to which VDD can be lowered without losing RAM data.

3: These parameters are characterized but not tested in manufacturing.

4: VDD Core voltage must remain at VSS for a minimum of 200 µs to ensure POR.

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