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PIC24HJ128GP310 Datasheet(PDF) 158 Page - Microchip Technology |
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PIC24HJ128GP310 Datasheet(HTML) 158 Page - Microchip Technology |
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158 / 286 page  PIC24HJXXXGPX06/X08/X10 DS70175F-page 156 © 2007 Microchip Technology Inc. 16.11 Slope Control The I2C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate con- trol if desired. It is necessary to disable the slew rate control for 1 MHz mode. 16.12 Clock Arbitration Clock arbitration occurs when the master deasserts the SCLx pin (SCLx allowed to float high) during any receive, transmit or Restart/Stop condition. When the SCLx pin is allowed to float high, the Baud Rate Gen- erator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of I2CxBRG and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device. 16.13 Multi-Master Communication, Bus Collision and Bus Arbitration Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a ‘1’ on SDAx by letting SDAx float high while another master asserts a ‘0’. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the I2C master events interrupt flag and reset the master portion of the I2C port to its Idle state. |
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