AM79C32AVC datasheet(50/101 Pages) AMD

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Am79C30A/32A Data Sheet

DSC/IDC Circuit IOM-2 Terminal Mode

Implementation

Data Channels

The B1 and B2 channels are physically the first two

8-bit time slots after the frame sync pulse. When mak-

ing a MUX connection to these channels, IOM-2 chan-

nels B1 and B2 correspond to MUX channels Bd and

Be, respectively. When in an IOM-2 mode, a MUX con-

nection to channel Bf provides access to one of the two

intercommunication channels as selected in PPCR1.

Command/Indicate Channels

The Peripheral Port supports the C/I channels of the

first and second IOM-2 subframes. The Peripheral Port

monitors these two channels, and generates an inter-

rupt any time the received data changes and is stable

for two frames. The received data is read from C/I Re-

ceive Data Register 0 or 1, and C/I transmit data is writ-

ten to C/I Transmit Data Register 0 or 1. When the TIC

bus feature is enabled, C/I0 transmit access to the

IOM-2 Interface is controlled by CITDR0 bit 7, Bus Ac-

cess Request.

D Channel

If the peripheral Port is configured as IOM-2 master

with TIC bus disabled, the DLC will transmit and re-

ceive D-channel data to and from the S Interface

through the LIU. The D-channel data received from the

S Interface is also output on the IOM-2 Interface.

D-channel data received from the IOM-2 Interface is

disregarded. If, however, TIC bus is enabled, the TIC

bus control logic will arbitrate D-channel data flow be-

tween the S Interface and either the DLC or IOM-2 In-

terface based on TIC bus access procedures.

When the Peripheral Port is configured as IOM-2 slave,

the DLC will transmit and receive D-channel data to

and from the IOM-2 Interface. This will be a dedicated

path if the TIC bus feature is disabled, or with DLC ac-

cess arbitrated according to TIC bus access proce-

dures if the TIC bus feature is enabled. The LIU is not

used in this situation, so there is no D-channel data

flow between the DLC and LIU.

Monitor Channels

Support for the two Monitor channels is provided on a

one-at-a-time basis. A bit in Peripheral Port Control

nels is utilized at any time.

TIC Bus

The IOM-2 TIC bus control bits reside in the last byte to

the IOM-2 Terminal mode frame (channel 2, byte 4).

The bits and their definitions are shown in Figure 7

Data Upstream (output)

Data Downstream (input)

BAC

TBA2 TBA1 TBA0

S/G

A/B

Notes:

BAC bit (Bus Accessed): indication to other devices that the TIC bus is being accessed. When 0 the bus is accessed, when 1 it

is free. This bit is driven to zero by the device that gets an address match on the TBA2–0 bits.

TBA2–0 bits (TIC Bus Address): address bit used for arbitration of TIC bus control Assumes Open–Drain bus such that device

with highest zero content in its address has the highest priority. Lowest priority address, which is also the default, is 111.

E-bits (Echo): D-channel Echo bits from the S-bus. Will not be supported by the DSC.

S/G bit (Stop/Go): used to indicate availability of the S-bus D-channel. When 0, the D-channel is clear for transmission. When

1, D-channel transmission should be halted.

A/B bit (Available/Blocked): supplementary bit for D-channel control. 1 indicates D-channel available, 0 D-channel blocked.

Optional, will not be supported by the DSC.

Figure 7.

TIC Bus Control Bits and Definitions

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