AM79C974 datasheet(21/153 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C974

The PCnet-SCSI controller monitors the

PERR input

during a bus master write cycle. It will assert the Data

Parity Reported bit in the Status register of the Configu-

ration Space when a parity error is reported by the target

device.

When

RST is active, PERR is an input for NAND tree

testing.

REQA

Bus Request

Input/Output, Active Low

The Am79C974’s SCSI controller asserts

REQA pin as

a signal that it wishes to become a bus master. Once as-

serted,

REQA remains active until GNTA has become

active.

When

RST is active, REQA is an input for NAND tree

testing. This is the only time

REQA is an input.

REQB

Bus Request

Input/Output, Active Low

The Am79C974’s Ethernet controller asserts

REQB pin

as a signal that it wishes to become a bus master. Once

asserted,

REQB remains active until GNT has become

active, independent of subsequent assertion of

SLEEP

or setting of the STOP bit or access to the S_RESET

port (offset 14h).

When

RST is active, REQB is an input for NAND tree

testing. This is the only time

REQB is an input.

RST

Reset

Input, Active Low

When

RST is asserted low, then the PCnet-SCSI con-

troller performs an internal system reset of the type

H_RESET (HARDWARE_RESET).

RST must be held

for a minimum of 30 CLK periods. While in the H_RE-

SET state, the PCnet-SCSI controller will disable or

deassert all outputs.

RST may be asynchronous to the

CLK when asserted or deasserted. It is recommended

that the deassertion be synchronous to guarantee a

clean and bounce free edge.

When

RST is active, NAND tree testing is enabled. All

PCI interface pins are in input mode. The result of the

NAND tree testing can be observed on the

BUSY output

(pin 62).

SERR

System Error

Input/Output, Active Low, Open Drain

This signal is asserted for one CLK by the PCnet-SCSI

controller when it detects a parity error during the ad-

dress phase when its AD[31:00] lines are inputs.

The

SERR pin is only active when SERREN (bit 8) and

PERREN (bit 6) in the PCI command register are set.

When

RST is active, SERR is an input for NAND tree

testing.

STOP

Stop

Input/Output, Active Low

In the slave role, the PCnet-SCSI controller drives the

STOP signal to inform the bus master to stop the current

transaction. In the bus master role, the PCnet-SCSI

controller receives the

STOP signal and stops the cur-

rent transaction.

When

RST is active, STOP is an input for NAND tree

testing.

TRDY

Target Ready

Input/Output, Active Low

This signal indicates the PCnet-SCSI controller’s ability

as a selected device to complete the current data phase

of the transaction.

TRDY is used in conjunction with the

IRDY. A data phase is completed on any clock both

TRDY and IRDY are asserted. During a read TRDY indi-

cates that valid data is present on AD[31:00]. During a

write,

TRDY indicates that data has been accepted.

Wait states are inserted until both

IRDY and TRDY are

asserted simultaneously.

When

RST is active, TRDY is an input for NAND tree

testing.

Ethernet Controller Pins

Board Interface

LED1

Output

This pin is shared with the EESK function. As

LED1, the

function and polarity of this pin are programmable

through BCR5. By default,

LED1 is active LOW and it in-

dicates receive activity on the network. The

LED1 output

from the PCnet-SCSI controller is capable of sinking the

12 mA of current necessary to drive an LED directly.

The

LED1 pin is also used during EEPROM Auto-detec-

tion to determine whether or not an EEPROM is present

at the PCnet-SCSI controller Microwire interface. At the

trailing edge of the

RST pin, LED1 is sampled to deter-

mine the value of the EEDET bit in BCR19. A sampled

HIGH value means that an EEPROM is present, and

EEDET will be set to ONE. A sampled LOW value

means that an EEPROM is not present, and EEDET will

be set to ZERO. See the EEPROM Auto-detection sec-

tion for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead, in or-

der to resolve the EEDET setting.

AM79C974 Datasheet(PDF) 21 Page - Advanced Micro Devices

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