AM79C983A datasheet(39/60 Pages) AMD

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Am79C983A

PRELIMINARY

Pn/AUI/RAUI/EP

Last

Source

Address

Lock

disabled

Last

Source

Address

Lock

enabled

Note: Setting a bit on this register invalidates the cor-

responding Source Address Changes Register.

These registers are accessed by writing 0000 0100 to

the C register.

Partitioning Status of Ports

Address:

1110 0000

These bits indicate the partition status of the corre-

sponding ports. Ports that are partitioned will transmit

packets. However, the IMR2 device will not repeat

packets received by a partitioned port.

Pn/AUI/RAUI

Port partitioned

Port connected

Link Test Status of Ports

Address:

1110 0010

The register bits indicate the Link Test Status of the cor-

responding ports. The bit setting is based on data re-

ceived by the QuIET device. Therefore, the bit setting is

invalid if a non-QuIET transceiver is used for the port.

TPn/SPn

Link Test failed

Link Test passed

Loopback Error Status

Address:

1110 0011

When a packet is transmitted, the DO signal is looped

back to the IMR2 device through the corresponding DI

pins. When a bit on this register is set, data is not being

looped back to the IMR2 device.

Pn/AUI/RAUI

No Loopback Error

Loopback Error

Note: The RAUI bit is not valid when the RAUI port is

in the reverse mode.

Receive Polarity Status

Address:

1110 0100

Each register bit represents the receive polarity status

of the corresponding port. The bit setting is based on

data received from the QuIET device through the serial

interface. If another transceiver device is used, the bit

setting reﬂects what is on the corresponding SDATA.

TPn/SPn

Polarity correct

Polarity reversed

SQE Test Status

Address:

1110 0101

These register bits reﬂect the status of the last packet

received from the corresponding port. The RAUI bit is

not valid when the RAUI port is in the reverse mode.

Pn/AUI/RAUI

No SQE Test Error

SQE Test Error

The RMON registers can be accessed by writing to ad-

dress 0000 0101 and then accessing the individual reg-

isters. The RMON registers are 32-bit counters and

comply with etherStatsEntry of the statistics group of

the RMON MIB (RFC 1757) or etherHistoryEntry of the

History group of RFC 1757. They are 4 bytes long and

are read low order byte to high order byte.

The RMON registers can usually only be read. How-

ever, they can be written to when the Repeater Reset

bit or the Management Reset bit on the Device Conﬁg-

uration Register is set.

etherStatsOctets

Address:

1110 0000

The value in this register represents the total number of

octets received (excluding preamble bits, but including

FCS bits) by the IMR2 device.

etherStatsPkts

Address:

1110 0001

The value in this register represents the total number of

packets received by the IMR2 device.

RAUI

AUI P11 P10 P9

D Port Read

Byte 0

Byte 1

LSB

MSB

TP7

TP6 TP5

TP4

TP3

TP2

TP1

TP0

SP3 SP2 SP1 SP0 TP11

TP9 TP8

Byte 0

Byte 1

D Port Read

LSB

MSB

TP10

RAUI

AUI P11 P10 P9

D Port Read

Byte 0

Byte 1

MSB

LSB

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

SP3 SP2 SP1 SP0 TP11 TP10 TP9 TP8

Byte 0

Byte 1

D Port Read

LSB

MSB

RAUI

AUI P11 P10 P9

D Port Read

Byte 0

Byte 1

MSB

LSB

AM79C983A Datasheet(PDF) 39 Page - Advanced Micro Devices

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