ADC10158CIWMXSLASHNOPB datasheet(21/25 Pages) TI

21 / 25 page

2.0 Applications Information

(Continued)

voltage which is necessary to just cause an output digital

code transition from 000 0000 0000 to 000 0000 0001

(10-bits plus sign) and the ideal 1⁄2 LSB value (1⁄2 LSB = 2.44

mV for V

REF = + 5.000V and 10-bit plus sign resolution).

The zero error of the A/D does not require adjustment. If the

minimum analog input voltage value, V

IN(Min), is not ground,

the effetive “zero” voltage can be adjusted to a convenient

value. The converter can be made to output an all zeros

digital code for this minimum input voltage by biasing any

minus input to V

IN(Min). This is useful for either the differen-

tial or pseudo-differential input channel configurations.

2.4.2 Full-Scale

The full-scale adjustment can be made by applying a differ-

ential input voltage which is 11⁄2 LSB down from the desired

analog full-scale voltage range and then adjusting the V

REF

voltage (V

REF =VREF

+ −V

REF

−) for a digital output code

changing from 011 1111 1110 to 011 1111 1111. In bipolar

signed operation this only adjusts the positive full scale error.

The negative full-scale error will be as specified in the Elec-

trical Characteristics after a positive full-scale adjustment.

2.4.3 Adjusting for an Arbitrary Analog Input

Voltage Range

If the analog zero voltage of the A/D is shifted away from

ground (for example, to accommodate an analog input signal

which does not go to ground), this new zero reference

should be properly adjusted first. A plus input voltage which

equals this desired zero reference plus 1⁄2 LSB (where the

LSB is calculated for the desired analog span, using 1 LSB =

analog span/2

n, n being the programmed resolution) is ap-

plied to selected plus input and the zero reference voltage at

the corresponding minus input should then be adjusted to

just obtain the 000

HEX to 001HEX code transition.

The full-scale adjustment should be made [with the proper

minus input voltage applied] by forcing a voltage to the plus

input which is given by:

where V

MAX equals the high end of the ananlog input range,

MIN equals the low end (the offset zero) of the analog range

and n equals the programmed resolution. Both V

MAX and

MIN are ground referred. The VREF (VREF =VREF

+ −V

REF

−)

voltage is then adjusted to provide a code change from

3FE

HEX to 3FFHEX. Note, when using a pseudo-differential

or differential multiplexer mode where V

REF

+ and V

REF− are

placed within the V

+ and V− range, the individual values of

REF

+ and V

REF

− do not matter, only the difference sets the

analog input voltage span. This completes the adjustment

procedure.

2.5 INPUT SAMPLE-AND-HOLD

The ADC10154/8’s sample/hold capacitor is implemented in

the capacitor array. After the channel address is loaded, the

array is switched to sample the selected positive analog

input. The rising edge of WR loads the multiplexer address-

ing information. The sampling period for the assigned posi-

tive input is maintained for the duration of the acquisition

time (t

A), i.e., approximately 6 to 8 clock cycles after the

rising edge of WR.

An acquisition window of 6 clock cycles is available to allow

the voltage on the capacitor array to settle to the positive

analog input voltage. Any change in the analog voltage on a

selected positive input before or after the acquisition window

will not effect the A/D conversion result.

In the simplest case, the array’s acquisition time is deter-

mined by the R

ON (9 kΩ) of the multiplexer switches, the

stray input capacitance C

S1 (3.5 pF) and the total array (CL)

and stray (C

S2) capacitance (CL +CS2 = 48 pF). For a large

source resistance the analog input can be modeled as an

RC network as shown in

Figure 6. The values shown yield an

acquisition time of about 1.1 µs for 10-bit unipolar or 10-bit

plus sign bipolar accuracy with a zero-to-full-scale change in

the input voltage. External source resistance and capaci-

tance will lengthen the acquisition time and should be ac-

counted for. Slowing the clock will lengthen the acquisition

time, thereby allowing a larger external source resistance.

The curve “Signal to Noise Ratio vs. Output Frequency”

(

Figure 7) gives an indication of the usable bandwidth of the

ADC10154/ADC10158. The signal-to-noise ratio of an ideal

A/D is the ratio of the RMS value of the full scale input signal

amplitude to the value of the total error amplitude (including

noise) caused by the transfer function of the A/D. An ideal

10-bit plus sign A/D converter with a total unadjusted error of

0 LSB would have a signal-to-noise ratio of about 68 dB,

which can be derived from the equation:

S/N = 6.02(n) + 1.76

where S/N is in dB and n is the number of bits.

Figure 3

shows the signal-to-noise ratio vs. input frequency of a typi-

cal ADC10154/ADC10158 with 1⁄2 LSB total unadjusted er-

ror. The dotted lines show signal-to-noise ratios for an ideal

(noiseless) 10-bit A/D with 0 LSB error and an A/D with a 1

LSB error.

DS011225-23

FIGURE 6. Analog Input Model

SNR vs Input Frequency

DS011225-24

FIGURE 7. ADC10154/ADC10158

Signal-to-Noise Ratio vs Input Frequency

ADC10158CIWMX/NOPB Datasheet(PDF) 21 Page - Texas Instruments

ADC10158CIWMX/NOPB Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL