MACH211SP-7VC datasheet(28/37 Pages) AMD

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MACH211SP-7/10/12/15/20

FMAX PARAMETERS

The parameter fMAX is the maximum clock rate at which

the device is guaranteed to operate. Because the ﬂexi-

bility inherent in programmable logic devices offers a

choice of clocked ﬂip-ﬂop designs, fMAX is speciﬁed for

three types of synchronous designs.

The ﬁrst type of design is a state machine with feed-

back signals sent off-chip. This external feedback could

go back to the device inputs, or to a second device in a

multi-chip state machine. The slowest path deﬁning the

period is the sum of the clock-to-output time and the

input setup time for the external signals (tS + tCO). The

reciprocal, fMAX, is the maximum frequency with exter-

nal feedback or in conjunction with an equivalent speed

device. This fMAX is designated “fMAX external.”

The second type of design is a single-chip state ma-

chine with internal feedback only. In this case, ﬂip-ﬂop

inputs are deﬁned by the device inputs and ﬂip-ﬂop out-

puts. Under these conditions, the period is limited by

the internal delay from the ﬂip-ﬂop outputs through the

internal feedback and logic to the ﬂip-ﬂop inputs. This

fMAX is designated “fMAX internal”. A simple internal

counter is a good example of this type of design; there-

fore, this parameter is sometimes called “fCNT.”

The third type of design is a simple data path applica-

tion. In this case, input data is presented to the ﬂip-ﬂop

and clocked through; no feedback is employed. Under

these conditions, the period is limited by the sum of the

data setup time and the data hold time (tS + tH). How-

ever, a lower limit for the period of each fMAX type is the

minimum clock period (tWH + tWL). Usually, this mini-

mum clock period determines the period for the third

fMAX, designated “fMAX no feedback.”

For devices with input registers, one additional fMAX pa-

rameter is speciﬁed: fMAXIR. Because this involves no

feedback, it is calculated the same way as fMAX no

feedback. The minimum period will be limited either by

the sum of the setup and hold times (tSIR + tHIR) or the

sum of the clock widths (tWICL + tWICH). The clock

widths are normally the limiting parameters, so that

fMAXIR is speciﬁed as 1/(tWICL + tWICH). Note that if both

input and output registers are use in the same path, the

overall frequency will be limited by tICS.

All frequencies except fMAX internal are calculated from

other measured AC parameters. fMAX internal is mea-

sured directly.

tSIR

CLK

LOGIC

CLK

LOGIC

CLK

LOGIC

fMAX External; 1/(tS + tCO)fMAX Internal (fCNT)

fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)

tCO

CLK

LOGIC

(SECOND

CHIP)

tHIR

20405B-21

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