L9777

Block diagrams and pins configuration

Doc ID 13496 Rev 2

5/25

1

Block diagrams and pins configuration

1.1

Block diagram (option A)

Figure 1.

Block diagram (option A)

1.2

Option B features

●

VDD can sustain short to 40 V regardless of VI battery voltage

●

Current capability of VDD scaled down to 50 mA with dropout of 1.5 V (Max.)

●

In default condition, VDD and WD functions are disabled using 2 pull down current on

VDD_EN and WD_EN pin

●

Standby current consumption reduced to 100 µA (Typ.)

Figure 2.

Package pin configuration (options A and B)

watchdog

VI

Vbatt

WD

D

TIMING

NMI

WD_EN

GND

VCC

IVCC=200mA

Voltage

Reference

Low

Voltage

Reset

Start up

3R

R

VOFF

+

_

1.26V

RESET

IWD_EN

RADJ

Delay

VDD_EN

VDD

RNMI

RRESET

RWD

IVDD=100mA

VMUXTH

10

IVDD_EN

VCC

RESET

NMI

D

VDD_EN

WD

WD_EN

VI

TIMING

VCC

VDD

GND

RADJ

1

3

2

4

5

6

10

9

8

7

11

12

PinConfA_B