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STM8L051F3P6 Datasheet(PDF) 22 Page - STMicroelectronics

Part # STM8L051F3P6
Description  Value line, 8-bit ultralow power MCU, 8-KB Flash
PDF  46 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8L051F3P6 Datasheet(HTML) 22 Page - STMicroelectronics

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Pin description
STM8L051F3
22/46
Doc ID 022985 Rev 1
Note:
The slope control of all GPIO pins, except true open drain pins, can be programmed. By
default, the slope control is limited to 2 MHz.
17 PB7/SPI1_MISO/ADC1_IN11
I/O X
XX HS X
X Port B7
SPI1 master in- slave out/
ADC1_IN11
18 PC0/I2C_SDA
I/O X
XT(4)
Port C0 I2C data
19 PC1/I2C_SCL
I/O X
XT(3)
Port C1 I2C clock
20
PC4/USART_CK]/
I2C_SMB/CCO/ADC1_IN4
I/O X
XX HS X
X Port C4
USART synchronous clock /
I2C1_SMB / Configurable clock
output / ADC1_IN4
1
PC5/OSC32_IN /[SPI1_NSS](2)/
[USART_TX](2)/TIM2_CH1
I/O X
XX HS X
X Port C5
LSE oscillator input / [SPI
master/slave select] / [USART
transmit]/Timer 2 -channel 1
2
PC6/OSC32_OUT/[SPI_SCK](2)/[
USART_RX](2)/TIM2_CH2
I/O X
XX HS X
X Port C6
LSE oscillator output / [SPI clock] /
[USART receive]/
Timer 2 -channel 2
9
PD0/TIM3_CH2/[ADC1_TRIG](2)/
ADC1_IN22
I/O X
XX HS X
X Port D0
Timer 3 - channel 2 / [ADC1_Trigger]
/ ADC1_IN22
8VDD / VDDA / VREF+
S
Digital supply voltage /
ADC1 positive voltage reference
7VSS / VREF- / VSSA
Ground voltage / ADC1 negative voltage
reference / Analog ground voltage
3
PA0(5)/[USART_CK](2)/
SWIM/BEEP/IR_TIM (6)
I/O X
X
X
HS
(6)
XX Port A0
[USART1 synchronous clock](2) /
SWIM input and output /
Beep output / Infrared Timer output
1.
At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15xxx and STM8L16xxx reference manual (RM0031).
2.
[ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
3.
A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
4.
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented).
5.
The PA0 pin is in input pull-up during the reset phase and after reset release.
6.
High Sink LED driver capability available on PA0.
Table 4.
Low density value line STM8L05xxx pin description (continued)
pin
n°
Pin name
Input
Output
Default alternate function



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