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L9D232M64SBG5 Datasheet(PDF) 97 Page - LOGIC Devices Incorporated |
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L9D232M64SBG5 Datasheet(HTML) 97 Page - LOGIC Devices Incorporated |
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97 / 115 page ![]() DO CK CK# Command DQ DQS, DQS# RL = 3 T0 T1 T2 Don’t Care Transitioning Data NOP NOP T3 T4 T5 Valid T6 T7 tCKE (MIN) Address A10 NOP CKE READ Valid Power-down 2 or self refresh entry NOP 1 Valid DO DO DO Notes: 1.In the example shown, READ burst completes at T5; earliest power-down or self refresh entry is at T6. 2. Power-down or self refresh entry may occur after the READ burst completes. CK CK# Command DQ DQS, DQS# RL = 3 T0 T1 T2 Don’t Care Transitioning Data NOP NOP T3 T4 T5 Valid Valid T6 T7 t CKE (MIN) Address A10 NOP CKE READ Valid Power-down or self refresh 2 entry NOP1 DO DO DO DO Notes: 1. In the example shown, READ burst completes at T5; earliest power-down or self refresh entry is at T6. 2. Power-down or self refresh entry may occur after the READ burst completes. LOGIC Devices Incorporated www.logicdevices.com September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E 2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD) L9D232M64SBG5 L9D232M72SBG5 L9D232M80SBG5 L9D264M64SBG5 L9D264M72SBG5 L9D264M80SBG5 High Performance, Integrated Memory Module Product FIGURE 63 - READ-TO-POWER-DOWN OR SELF REFRESH ENTRY FIGURE 64 - READ WITH AUTO PRECHARGE-TO-POWER-DOWN OR SELF REFRESH ENTRY |
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