PIC24FJ128GA310 datasheet(205/406 Pages) MICROCHIP

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DS39996F-page 205

PIC24FJ128GA310 FAMILY

14.0

INPUT CAPTURE WITH

DEDICATED TIMERS

Devices in the PIC24FJ128GA310 family contain

seven independent input capture modules. Each of the

modules offers a wide range of configuration and

operating options for capturing external pulse events

and generating interrupts.

Key features of the input capture module include:

• Hardware configurable for 32-bit operation in all

modes by cascading two adjacent modules

• Synchronous and Trigger modes of output

compare operation, with up to 30 user-selectable

sync/trigger sources available

• A 4-level FIFO buffer for capturing and holding

timer values for several events

• Configurable interrupt generation

• Up to 6 clock sources available for each module,

driving a separate internal 16-bit counter

The module is controlled through two registers:

ICxCON1 (Register 14-1) and ICxCON2 (Register 14-2).

A general block diagram of the module is shown in

Figure 14-1.

14.1

General Operating Modes

14.1.1

SYNCHRONOUS AND TRIGGER

MODES

When the input capture module operates in a

Free-Running mode, the internal 16-bit counter,

ICxTMR, counts up continuously, wrapping around

from FFFFh to 0000h on each overflow. Its period is

synchronized to the selected external clock source.

When a capture event occurs, the current 16-bit value

of the internal counter is written to the FIFO buffer.

In Synchronous mode, the module begins capturing

events on the ICx pin as soon as its selected clock

source is enabled. Whenever an event occurs on the

selected sync source, the internal counter is reset. In

Trigger mode, the module waits for a Sync event from

another internal module to occur before allowing the

internal counter to run.

Standard, free-running operation is selected by setting

the SYNCSEL bits (ICxCON2<4:0>) to ‘00000’ and

clearing the ICTRIG bit (ICxCON2<7>). Synchronous

and Trigger modes are selected any time the

SYNCSEL bits are set to any value except ‘00000’.

The ICTRIG bit selects either Synchronous or Trigger

mode; setting the bit selects Trigger mode operation. In

both modes, the SYNCSEL bits determine the

sync/trigger source.

When the SYNCSEL bits are set to ‘00000’ and

ICTRIG is set, the module operates in Software Trigger

mode. In this case, capture operations are started by

manually setting the TRIGSTAT bit (ICxCON2<6>).

FIGURE 14-1:

INPUT CAPTURE BLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section

34.

“Input

Capture

with

Dedicated Timer”

(DS39722). The infor-

mation in this data sheet supersedes the

information in the FRM.

Note 1:

The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral Pin Select

(PPS)”

for more information.

ICXBUF

4-Level FIFO Buffer

ICX Pin(1)

ICM<2:0>

Set ICXIF

Edge Detect Logic

ICI1<:0>

ICOV, ICBNE

Interrupt

Logic

System Bus

Prescaler

Counter

1:1/4/16

and

Clock Synchronizer

Event and

Clock

Select

IC Clock

Sources

Sync and

ICTSEL<2:0>

SYNCSEL<4:0>

Trigger

Increment

Reset

Sync and

Trigger

Logic

Trigger Sources

ICXTMR

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