PIC24FJ128GA310 datasheet(224/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 224

 2010-2011 Microchip Technology Inc.

SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R-0, HSC

SPIEN(1)

—

SPISIDL

—

SPIBEC2

SPIBEC1

SPIBEC0

bit 15

bit 8

R-0, HSC

R/C-0, HS

R-0, HSC

R/W-0

R-0, HSC

SRMPT

SPIROV

SRXMPT

SISEL2

SISEL1

SISEL0

SPITBF

SPIRBF

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

HSC = Hardware Settable/Clearable bit

bit 15

SPIEN:

SPIx Enable bit(1)

= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

= Disables module

bit 14

Unimplemented:

Read as ‘0’

bit 13

SPISIDL:

Stop in Idle Mode bit

= Discontinue module operation when device enters Idle mode

= Continue module operation in Idle mode

bit 12-11

Unimplemented:

Read as ‘0’

bit 10-8

SPIBEC<2:0>:

SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7

SRMPT:

Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)

= SPIx Shift register is empty and ready to send or receive

= SPIx Shift register is not empty

bit 6

SPIROV:

Receive Overflow Flag bit

= A new byte/word is completely received and discarded

The user software has not read the previous data in the SPIxBUF register.

= No overflow has occurred

bit 5

SRXMPT:

Receive FIFO Empty bit (valid in Enhanced Buffer mode)

= Receive FIFO is empty

= Receive FIFO is not empty

bit 4-2

SISEL<2:0>:

SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111

= Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)

110

= Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty

101

= Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete

100

= Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot

011

= Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)

010

= Interrupt when the SPIx receive buffer is 3/4 or more full

001

= Interrupt when data is available in the receive buffer (SRMPT bit is set)

000

= Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT

bit is set)

Note 1:

If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4

“Peripheral Pin Select (PPS)”

for more information.

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