PIC24FJ128GA310 datasheet(238/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 238

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I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC

U-0

R/C-0, HS

R-0, HSC

ACKSTAT

TRSTAT

—

BCL

GCSTAT

ADD10

bit 15

bit 8

R/C-0, HS

R-0, HSC R/C-0, HSC

R/C-0, HSC

R-0, HSC

IWCOL

I2COV

D/A

R/W

RBF

TBF

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

HSC = Hardware Settable/Clearable bit

bit 15

ACKSTAT:

Acknowledge Status bit

= NACK was detected last

= ACK was detected last

Hardware is set or cleared at the end of Acknowledge.

bit 14

TRSTAT:

Transmit Status bit

(when operating as I2C™ master; applicable to master transmit operation.)

= Master transmit is in progress (8 bits + ACK)

= Master transmit is not in progress

Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge.

bit 13-11

Unimplemented:

Read as ‘0’

bit 10

BCL:

Master Bus Collision Detect bit

= A bus collision has been detected during a master operation

= No collision

Hardware is set at the detection of a bus collision.

bit 9

GCSTAT:

General Call Status bit

= General call address was received

= General call address was not received

Hardware is set when the address matches the general call address; hardware is clear at Stop detection.

bit 8

ADD10:

10-Bit Address Status bit

= 10-bit address was matched

= 10-bit address was not matched

Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection.

bit 7

IWCOL:

Write Collision Detect bit

= An attempt to write to the I2CxTRN register failed because the I2C module is busy

= No collision

Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software).

bit 6

I2COV:

Receive Overflow Flag bit

= A byte was received while the I2CxRCV register is still holding the previous byte

= No overflow

Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5

D/A:

Data/Address bit (when operating as I2C slave)

= Indicates that the last byte received was data

= Indicates that the last byte received was a device address

Hardware is clear at the device address match. Hardware is set after a transmission finishes or by

reception of a slave byte.

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