PIC24FJ128GA310 datasheet(246/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 246

 2010-2011 Microchip Technology Inc.

UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

U-0

R/W-0 HC

R/W-0

R-0, HSC

R-1, HSC

UTXISEL1

UTXINV(1)

UTXISEL0

—

UTXBRK

UTXEN(2)

UTXBF

TRMT(3)

bit 15

bit 8

R/W-0

R-1, HSC

R-0, HSC

R/C-0, HS

R-0, HSC

URXISEL1

URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 7

bit 0

Legend:

C = Clearable bit

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

HS = Hardware Settable bit

HC = Hardware Clearable bit

bit 15,13

UTXISEL<1:0>:

Transmission Interrupt Mode Selection bits

= Reserved; do not use

= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the

transmit buffer becomes empty

= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least

one character open in the transmit buffer)

bit 14

UTXINV:

IrDA® Encoder Transmit Polarity Inversion bit(1)

IREN = 0:

= UxTX is Idle ‘0’

= UxTX is Idle ‘1’

IREN = 1:

= UxTX is Idle ‘1’

= UxTX is Idle ‘0’

bit 12

Unimplemented:

Read as ‘0’

bit 11

UTXBRK:

Transmit Break bit

= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

= Sync Break transmission is disabled or completed

bit 10

UTXEN:

Transmit Enable bit(2)

= Transmit is enabled, UxTX pin is controlled by UARTx

= Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is

controlled by the port.

bit 9

UTXBF:

Transmit Buffer Full Status bit (read-only)

= Transmit buffer is full

= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT:

Transmit Shift Register Empty bit (read-only)(3)

= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

= Transmit Shift Register is not empty, a transmission is in progress or queued

Note 1:

The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled

(IREN = 1).

If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See

Section 11.4 “Peripheral Pin Select (PPS)”

for more information.

The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.

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