PIC24FJ128GA310 datasheet(247/406 Pages) MICROCHIP

247 / 406 page

 2010-2011 Microchip Technology Inc.

DS39996F-page 247

PIC24FJ128GA310 FAMILY

bit 7-6

URXISEL<1:0>:

Receive Interrupt Mode Selection bits

= Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters)

= Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;

receive buffer has one or more characters

bit 5

ADDEN:

Address Character Detect bit (bit 8 of received data = 1)

= Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)

= Address Detect mode is disabled

bit 4

RIDLE:

Receiver Idle bit (read-only)

= Receiver is Idle

= Receiver is active

bit 3

PERR:

Parity Error Status bit (read-only)

= Parity error has been detected for the current character (character at the top of the receive FIFO)

= Parity error has not been detected

bit 2

FERR:

Framing Error Status bit (read-only)

= Framing error has been detected for the current character (character at the top of the receive FIFO)

= Framing error has not been detected

bit 1

OERR:

Receive Buffer Overrun Error Status bit (clear/read-only)

= Receive buffer has overflowed

= Receive buffer has not overflowed (clearing a previously set OERR bit (1

 0 transition); will reset

the receiver buffer and the RSR to the empty state

bit 0

URXDA:

Receive Buffer Data Available bit (read-only)

= Receive buffer has data, at least one more character can be read

= Receive buffer is empty

UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

Note 1:

The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled

(IREN = 1).

If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See

Section 11.4 “Peripheral Pin Select (PPS)”

for more information.

The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.

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