PIC24FJ128GA310 datasheet(155/406 Pages) MICROCHIP

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 2010-2011 Microchip Technology Inc.

DS39996F-page 155

PIC24FJ128GA310 FAMILY

10.0

POWER-SAVING FEATURES

The PIC24FJ128GA310 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked reduces consumed

power.

PIC24FJ128GA310 family devices manage power

consumption with five strategies:

• Instruction-Based Power Reduction Modes

• Hardware-Based Power Reduction Features

• Clock Frequency Control

• Software Controlled Doze Mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to

selectively tailor an application’s power consumption,

while still maintaining critical application features, such

as timing-sensitive communications.

10.1

Overview of Power-Saving Modes

In addition to full-power operation, otherwise known as

Run mode, the PIC24FJ128GA310 family of devices

offers three Instruction-Based, Power-Saving modes

and one Hardware-Based mode:

•Idle

• Sleep (Sleep and Low-Voltage Sleep)

• Deep Sleep

•VBAT (with and without RTCC)

All four modes can be activated by powering down dif-

ferent functional areas of the microcontroller, allowing

progressive reductions of operating and Idle power

consumption. In addition, three of the modes can be

tailored for more power reduction, at a trade-off of

some operating features. Table 10-1 lists all of the

operating modes, in order of increasing power savings.

Table 10-2 summarizes how the microcontroller exits

the different modes. Specific information is provided in

the following sections.

TABLE 10-1:

OPERATING MODES FOR PIC24FJ128GA310 FAMILY DEVICES

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended

comprehensive

reference source. For more information,

refer to the “PIC24F Family Reference

Manual”

, “Section 57. Power-Saving

Features with VBAT”

(DS30622).

Mode

Entry

Active Systems

Core

Peripherals

Data RAM

Retention

RTCC(1)

DSGPR0/

DSGPR1

Retention

Run (default)

N/A

YYY

Idle

Instruction

Sleep:

Sleep

Instruction

S(2)

Low-Voltage Sleep

Instruction +

RETEN bit

NS(2)

Deep Sleep:

Deep Sleep

Instruction +

DSEN bit +

NNN

VBAT:

with RTCC

Hardware

Note 1:

If RTCC is otherwise enabled in firmware.

A select peripheral can operate during this mode from LPRC or some external clock.

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