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PIC24FJ128GA310 Datasheet(PDF) 156 Page - Microchip Technology |
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PIC24FJ128GA310 Datasheet(HTML) 156 Page - Microchip Technology |
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156 / 406 page ![]() PIC24FJ128GA310 FAMILY DS39996F-page 156 2010-2011 Microchip Technology Inc. TABLE 10-2: EXITING POWER SAVING MODES 10.1.1 INSTRUCTION-BASED POWER-SAVING MODES Three of the power-saving modes are entered through the execution of the PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals, except RTCC and DSWDT. It also freezes I/O states and removes power to Flash memory and may remove power to SRAM. The assembly syntax of the PWRSAV instruction is shown in Example 10-1. Sleep and Idle modes are entered directly with a single assembler command. Deep Sleep requires an additional sequence to unlock and enable the entry into Deep Sleep, which is described in Section 10.4.1 “Entering Deep Sleep Mode” . Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. The features enabled with the low-voltage/retention regulator results in some changes to the way that Sleep mode behaves. See Section 10.3 “Sleep Mode”. 10.1.1.1 Interrupts Coincident with Power Save Instructions Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep/Deep Sleep or Idle mode has completed. The device will then wake-up from Sleep/Deep Sleep or Idle mode. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX Mode Exit Conditions Code Execution Resumes(2) Interrupts Resets RTCC Alarm WDT VDD Restore All INT0 All POR MCLR Idle Y Y Y Y Y Y Y N/A Next instruction Sleep (all modes) Y Y Y Y Y Y Y N/A Deep Sleep N Y N Y Y Y Y(1) N/A Reset vector VBAT N N N N N N N Y Reset vector Note 1: Deep Sleep WDT. 2: Code execution resumption is also valid for all the exit conditions; for example, a MCLR and POR exit will cause code execution from the Reset vector. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. To enter Deep Sleep, the DSCON<0> bit should be cleared before setting the DSEN bit, // Syntax to enter Sleep mode: PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode // //Synatx to enter Idle mode: PWRSAV #IDLE_MODE ; Put the device into IDLE mode // // Syntax to enter Deep Sleep mode: // First use the unlock sequence to set the DSEN bit (see Example 10-2) CLR DSCON CLR DSCON ; (repeat the command) BSET DSCON, #DSEN ; Enable Deep Sleep BSET DSCON, #DSEN ; Enable Deep Sleep (repeat the command) PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode |
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