LP61L1008 datasheet(9/13 Pages) AMICC

Part #	LP61L1008

Description	128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

PDF	13 Pages

Scroll/Zoom	100%

Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

Logo

9 / 13 page

LP61L1008 Series

(June, 2001, Version 2.0)

AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 2

(Chip Enable Controlled)

tWC

Address

DIN

tDH

tDW

(4)

tCW5

tAW

tWR3

DOUT

tWHZ7

tWP2

tCW5

tAS1

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE and a low WE .

3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle.

4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high

impedance state.

5. tCW is measured from the later of CE going low to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured

±500mV from steady state. This parameter is sampled and not 100% tested.

LP61L1008 Datasheet(PDF) 9 Page - AMIC Technology