STM8S103F2P3TR datasheet(52/113 Pages) STMICROELECTRONICS

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(2)To calculate P

Dmax(TA), use the formula PDmax =(TJmax- TA)/ΘJA (see Thermal characteristics ) with the

value for TJmax given in the previous table and the value for ΘJA given in Thermal characteristics.

(3)Τ

Jmax is given by the test limit. Above this value the product behavior is not guaranteed.

Figure 9: fCPUmax versus VDD

2.95

4.0

5.0

5.5

CPU (MHz)

Functionality guaranteed

@TA-40 to 125 °C

Supply voltage

Functionality

not

guaranteed

in this area

Table 20: Operating conditions at power-up/power-down

Unit

Max

Typ

Min

Conditions

Parameter

Symbol

μs/V

∞

VDD rise time rate

tVDD

∞

VDD fall time rate

(1)

1.7

VDD rising

Reset release delay

tTEMP

2.85

2.7

2.6

Power-on reset threshold

VIT+

2.8

2.65

2.5

Brown-out reset threshold

VIT-

Brown-out reset hysteresis

VHYS(BOR)

(1) Reset is always generated after a t

TEMP delay. The application must ensure that VDD is still above the

minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.

VCAP external capacitor

10.3.1

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the

VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit

the series inductance to less than 15 nH.

DocID15441 Rev 6

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Electrical characteristics

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