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STM8S103F2U6TR Datasheet(PDF) 81 Page - STMicroelectronics |
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STM8S103F2U6TR Datasheet(HTML) 81 Page - STMicroelectronics |
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81 / 113 page ![]() (1) Parameters are given by selecting 10 MHz I/O output frequency. (2) Data characterization in progress. (3) Values based on design simulation and/or characterization results, and not tested in production. (4) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (5) Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Figure 39: SPI timing diagram - slave mode and CPHA = 0 ai14134 CPHA= 0 MOSI I NPUT MISO OUT P UT CPHA= 0 MS B O UT M SB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 B I T1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) Figure 40: SPI timing diagram - slave mode and CPHA = 1 ai14135 CPHA=1 MOSI I NPUT MISO OUT P UT CPHA=1 MS B O UT M SB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 B I T1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 81/113 DocID15441 Rev 6 Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 |
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