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STM32L151VD Datasheet(PDF) 91 Page - STMicroelectronics |
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STM32L151VD Datasheet(HTML) 91 Page - STMicroelectronics |
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91 / 140 page  STM32L151xD STM32L152xD Electrical characteristics Doc ID 022027 Rev 6 91/140 Table 42. Synchronous multiplexed PSRAM write timings(1) 1. CL = 30 pF. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2*THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) THCLK + 4 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 5 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high TBD - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high TBD - ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns |
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