TLK2541

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SLLS779B

– JANUARY 2008 – REVISED APRIL 2008

Table 3. Transmit Data Controls

TXD[16]

TXD[17]

16 BIT PARALLEL INPUT FULL RATE WITH 8B/10B CODING

0

0

Valid data on TXD[0:7],

Valid data TXD[8:15]

0

1

Valid data on TXD[0:7],

K code on TXD[8:15]

1

0

K code on TXD[0:7],

Valid data on TXD[8:15]

1

1

K code on TXD[0:7],

K code on TXD[8:15]

TXD[16]

8 BIT PARALLEL INPUT HALF RATE WITH 8B/10B CODING

0

Valid data on TXD[0:7]

1

K code on TXD[0:7]

8B/10B Bypass Mode

When control pin CTRL0 and CTRL1 are both held low, the TLK2541 will bypass the integrated 8B/10B encode

logic and will serialize the parallel data as it is presented to the parallel bus without coding or modification. Data

is serialized least-significant bit first, so bit TXD[0] is the first bit to be transmitted and bit TXD[19] is the last bit

transmitted. For all other combinations of CTRL0 and CTRL1, the data path includes the integrated 8B/10B

encode logic. In this mode, bits TXD[0:7] are presented to the lower order encoder, and bit TXD[16] controls

whether this byte is coded as Dx.y or as Kx.y. If TXD[16] is low, then the data is coded as Dx.y. If TXD[16] is

high, then the data is coded as Kx.y. Bits TXD[8:15] are presented to the higher order encoder, and bit TXD[17]

controls whether the data is coded as Dx.y or Kx.y. When TXD[16] or TXD[17] are used to generate Dx.y codes,

all possible combinations of the data codes are valid. However, there are only 12 valid Kx.y codes defined by the

8B/10B coding definition. To generate one of these valid K codes, the proper data bit combination must be

presented on the data bus. For example, to generate a K28.5 on the lower order byte, bit TXD[16] is set to logic

‘1’ and bits TXD[0:7] are set to ‘10111100’. If the K control bit is set while the data bus is set for an undefined

Kx.y code (such as K0.9), then the output of the encoder is undefined and not specified to be valid. When either

CTRL0 or CTRL1 are set to logic

‘1’, data presented on the parallel bus TDX[0:17] is presented to the 8B/10B

encoders. TXD[18] and TXD[19] are ignored. When both CTRL0 and CTL1 are set to logic

‘1’ the data presented

on the TXD[0:17] bus is encoded and serialized, allowing the use of the TLK2541 for proprietary protocols built

around the 8B/10B coding standard. For Ethernet or FibreChannel protocols, the Gigabit Ethernet or

FibreChannel modes may be better suited for the application.

Gigabit Ethernet IDLE Correction Mode

The IDLE pattern described in the IEEE802.3 clause 36 specification requires the IDLE pattern to be generated

as either K28.5 D5.6 or as K28.5 D16.2 depending on the state of the 8B/10B current running disparity at the

time that the IDLE pattern is sent. If the integrated 8B/10B encoders are used, then there is no way for the host

device controlling the TLK2541 TXD[0:19] bus to know whether to send the D5.6 code or the D16.2 code on the

upper order byte. If the TLK2541 is to be used to generate valid Ethernet IDLE patterns while using the on board

8b/10b encoder, then the Gigabit Ethernet IDLE Correction mode should be enabled. In this mode, a K28.5

D16.2 idle may be presented to the transmit parallel bus for all idles, and the TLK2541 substitutes a D5.6 in

place of the D16.2 on those occasions where the current running disparity requires that a K28.5 D5.6 is the

proper IDLE to be generated. This mode is enabled when CTRL0 is 0 and CTRL1 is high.

FibreChannel End Of Frame Correction Mode

The EOF pattern described in the ANSI FC-PH FibreChannel specification requires the EOF pattern to be

generated as either K28.5 D21.4 D21.x D21.x or as K28.5 D21.5 D21.

× D21.x depending on the state of the

8B/10B current running disparity at the time that the EOF pattern is sent. If the integrated 8B/10B encoders are

used, then there is no way for the host device controlling the TLK2541 TXD[0:19] bus to know whether to send

one EOF code or the other EOF code. If the TLK2541 is to be used to generate valid FibreChannel EOF patterns

while using the on board 8b/10b encoder then the FibreChannel EOF correction mode should be enabled. In this

mode, a K28.5 D21.4 D21.x D21.x EOF is presented to the transmit parallel bus for all EOF ordered sets, and

the TLK2541 substitutes a D21.5 in place of the D21.4 on those occasions where a K28.5 D21.5 D21.

× D21.× is

the proper EOF to be generated. This mode is enabled when CTRL0 is 1 and CTRL1 is 0. The EOF correction

mode also corrects the EOF-invalid ordered sets by correcting a K28.5 D10.5 D21.

× D21.× ordered set to be a

K28.5 D10.4 D21.

× D21.× ordered set when necessary.

© 2008, Texas Instruments Incorporated

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