PIC32MX120F032C datasheet(49/320 Pages) MICROCHIP

49 / 320 page

TABLE 4-7:

UART1 AND UART2 REGISTER MAP

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6000 U1MODE(1)

31:16

—

0000

15:0

—SIDL

IREN

RTSMD

—

UEN<1:0>

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6010

U1STA(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA 0110

6020 U1TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6030 U1RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6040 U1BRG(1)

31:16

—

0000

15:0

Baud Rate Generator Prescaler

0000

6200 U2MODE(1)

31:16

15:0

—

0000

—SIDL

IREN

RTSMD

—

UEN<1:0>

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6210

U2STA(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA 0110

6220 U2TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6230 U2RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6240 U2BRG(1)

31:16

—

0000

15:0

Baud Rate Generator Prescaler

0000

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information.

PIC32MX120F032C Datasheet(PDF) 49 Page - Microchip Technology

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