MPC8347VRAGDB datasheet(27/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 11 shows the MII transmit AC timing diagram.

Figure 11. MII Transmit AC Timing Diagram

8.2.2.2

MII Receive AC Timing Specifications

Table 28 provides the MII receive AC timing specifications.

TX_CLK data clock rise (20%–80%)

tMTXR

1.0

—

4.0

TX_CLK data clock fall (80%–20%)

tMTXF

1.0

—

4.0

Note:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing

(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference

symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Table 28. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

RX_CLK clock period 10 Mbps

tMRX

—

400

—

RX_CLK clock period 100 Mbps

tMRX

—40—

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

10.0

—

Table 27. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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