ADMCF328BN datasheet(21/36 Pages) AD

21 / 36 page

ADMCF328

–21–

REV. A

WATCHDOG TIMER

The ADMCF328 incorporates a watchdog timer that can per-

form a full reset of the DSP and motor control peripherals in the

event of software error. The watchdog timer is enabled by writing a

timeout value to the 16-bit WDTIMER register. The timeout

value represents the number of CLKIN cycles required for the

watchdog timer to count down to zero. When the watchdog timer

reaches zero, a full DSP core and motor control peripheral reset

is performed. In addition, Bit 1 of the SYSSTAT register is set

so that after a watchdog reset, the ADMCF328 can determine

that the reset was due to the timeout of the watchdog timer

and not an external reset. Following a watchdog reset, Bit 1 of

the SYSSTAT register may be cleared by writing zero to the

WDTIMER register. This clears the status bit but does not

enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled

when the ﬁrst timeout value is written to the WDTIMER register.

To prevent the watchdog timer from timing out, the user must

write to the WDTIMER register at regular intervals (shorter than

the programmed WDTIMER period value). On all but the ﬁrst

write to WDTIMER, the particular value written to the register

is unimportant since writing to WDTIMER simply reloads the

ﬁrst value written to this register.

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF328 has nine programmable digital input/output

(PIO) pins that are all multiplexed with other functions. The nine

PIO lines PIO0–PIO8 are multiplexed with the serial port (Pins

PIO0/TFS1 to PIO5/RFS1), the CLKOUT (pin PIO6/CLKOUT)

and the auxiliary PWM outputs (Pins PIO7/AUX1 and PIO8/

AUX0). When conﬁgured as a PIO, each of these nine pins can

act as an input, output, or an interrupt source.

The operating mode of pins PIO0/TFS1 to PIO7/AUX1 is con-

trolled by the PIOSELECT register. This 8-bit register has a bit

for each input so that the mode of each pin may be selected indi-

vidually. Bit 0 of PIOSELECT controls the operation of the

PIO0/TFS1 pin. Bit 1 controls the PIO1/DT1 pin, etc. Setting

the appropriate bit in the PIOSELECT register causes the cor-

responding pin to be conﬁgured for PIO functionality. Clearing

the bit selects the alternate (SPORT, CLKOUT, or AUXPWM)

mode of the corresponding pin. Following power-on reset, all

bits of PIOSELECT are set such that PIO functionality is

selected. The operating mode of the PIO8/AUX0 pin is selected

by Bit 1 of the PIODATA1 register. In a manner identical to the

PIOSELECT register, setting this bit enables PIO functionality

(PIO8) while clearing the bit enables auxiliary PWM functional-

ity (AUX0).

Once PIO functionality has been selected for any or all of these

nine pins, the direction may be set by the 8-bit PIODIR0 regis-

ter (for PIO0 to PIO7) and the 1-bit PIODIR1 register (for PIO8).

Clearing any bit conﬁgures the corresponding PIO line as an

input while setting the bit conﬁgures it as an output. By default,

following a reset, all bits of PIODIR0 and PIODIR1 are cleared

conﬁguring the PIO lines as inputs.

The data of the PIO0 to PIO8 lines is controlled by the

PIODATA0 register (for PIO0 to PIO7) and Bit 0 of the

PIODATA1 register (for PIO8). These registers can be used to

read data from those PIO lines conﬁgured as inputs and write data

to those conﬁgured as outputs. Any of the nine pins that have been

conﬁgured for PIO functionality can be made to act as an interrupt

source by setting the appropriate bit of the PIOINTEN0 register

(for PIO0 to PIO7) or the PIOINTEN1 register (for PIO8). In

order to act as an interrupt source the pin must also be conﬁgured

as an input. An interrupt is generated upon a change of state

(low-to-high transition or high-to-low transition) on any input

that has been conﬁgured as an interrupt source. Following a

change of state event on any such input, the corresponding

bit is set in the PIOFLAG0 register (for PIO0 to PIO7) and

PIOFLAG1 (for PIO8) and a common PIO interrupt is gener-

ated. Reading the PIOFLAG0 and PIOFLAG1 registers permits

determining the interrupt source. Reading the PIOFLAG0 and

PIOFLAG1 registers automatically clears all bits of the registers.

Following power-on or reset, all bits of PIOINTEN0 and

PIOINTEN1 are cleared so that no interrupts are enabled.

Each PIO line has an internal pull-down resistor so that follow-

ing power-on or reset all nine lines are conﬁgured as input PIOs

and will be read as logic lows if left unconnected.

Multiplexing of PIO Lines

The PIO0–PIO5 lines are multiplexed on the ADMCF328 with

the functional lines of the serial port, SPORT1. Although the

PIOSELECT register permits individual selection of the function-

ality of each pin, certain restrictions apply when using SPORT1

for serial communications.

In general, when transmitting and receiving data on the DTI and

DRIB pins, respectively, the PIO0/TFS1 and PIO5/RFS1 pins

must also be selected for SPORT (TFS1 and RFS1) functional-

ity even if unframed communication is implemented. Therefore,

when using SPORT1 for any type of serial communication, the

minimal setting for PIOSELECT is 0xD8 (i.e., select DTI, DRIB,

RFS1 and TFS1, select PIO7, PIO6, PIO4, PIO3 as digital I/O).

If the serial port communications use an internally generated

SCLK1, the PIO3/SCLK1 pin may be used as a general-purpose

PIO line. When external SCLK mode is selected, the PIO/SCLK1

pin must be enabled as SCLK1 (PIOSELECT [3] = 0).

When the DRIB data receive line of SPORT1 is selected as

the data receive line (MODECTRL [4] = 1), the PIO4/DRIA

line may be used as a general-purpose PIO pin. When the DRIA

data receive line of SPORT1 is selected as the data receive line

(MODECTRL [4] = 0), the PIO2/DRIB line may be used as

a general-purpose PIO pin.

Table VIII. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF328

AUXILIARY PWM TIMERS

Parameter

Test Conditions

Min

Typ

Max

Unit

Resolution

Bits

PWM Frequency

10 MHz CLKIN

0.039

MHz

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